Why not set your rules to not allow the etch to go over an open area (voids, pin and via clearance)? It shouldn't be too hard to do. Just use rule areas under the bga and zcopy voids and make them route obstructs. I believe that should solve the problem.
Kevin McCowan Sr. PCB Designer TSI Telsys
-----------------------------------------------------------Hi guys
This is the situation, my intention is to provide clean ground/plane under certain high-speed signals, all OK but when I route them between bga's and bend them near vias, there is always a possiblity that the cline is routed over a void or anti-etch.
I can set the DRC from cline-via little higher which won't work under BGA's,
Is there is a way to set a DRC and or a skill program which will flag me the nets as errors which when routed over a void or cross the plane?
Regards,
Venkata
Regards
Venkata Ramanan
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