[PCB_FORUM] Re: Cadence Library Issue
- From: "Noble, Jan" <jan.noble@xxxxxxxxx>
- To: <icu-pcb-forum@xxxxxxxxxxxxx>
- Date: Tue, 15 Mar 2005 08:58:35 -0800
Hi Alan,
I can help you. Can you zip up the entire logic symbol (and associated
tab/ptf/ppt whatever files or the part entry from a global file) and
send it to me? I need to see the entire thing to debug it. I built those
things for years..... :-)
Jan Noble
EPSD Product Change Coordinator
Shasta C3/D2, Tiger2
Langley/Mullins
253-371-6197 - desk
253-416-0307 - pager
Those who cast the votes decide nothing. Those who count the votes
decide everything. -- Josef V. Stalin
March 2005.
Saluting G.I. Joe. Because 'Knowledge is Power'.
-----Original Message-----
From: Ritter, Alan [mailto:Alan.Ritter@xxxxxxxxxx]
Sent: Monday, March 14, 2005 11:55 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Cadence Library Issue
Running 14.2, I found a problem where the correct "PRIMITIVE" isn't
being
pulled from a chips.prt file as part of the compilation/packaging
process.
If you look at the final PRIMITIVE in the chips.prt file, it is for
RELAYDPDT_RKA11DZ12. However, the PRIMITIVE that gets pulled into the
pstchip.dat file is the first PRIMITIVE in the file, not the one
referred to
by the PACK_TYPE property that is on the relays in the schematic.
Obviously, since the pinouts are different, the design doesn't exactly
work
as intended...
Both the design and the library entry are "old", dating back 10 years or
so.
Both have been through the chdl_uprev process from Allegro V12 to V13,
and
further updated to 14.2, if that matters...
Anyone have any light to shed on this? I've opened up a case with my
friendly local Cadence aps engineer...we'll see what they have to
say...and
I'll try finding any useful references on sourcelink, but I figured if
this
is a common problem, somebody out on the list has already solved it and
can
chime in quicker than Cadence will...
/s/jar (alan.ritter@xxxxxxxxxx)
http://www.mtritter.org
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