Here are a couple of ideas how it happens yet not sure why it does not throw
errors when you package and net into the PCB.
If he made that off page symbol, and attached a wire and named it (or more
likely cut and pasted it from the destination page) THEN made the connection to
USB0VBUS I can see that it would happen. Curious, what happens when you click
on wire segments and check properties, what net does it report?
From: dcarrow@xxxxxxxxxx
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Cadence Design Entry HDL Checker
Date: Fri, 31 Aug 2012 18:56:07 +0000
My engineer accidently placed two signal names on the same net(see R1 below).
This seems like a basic error but Cadence(Design Entry HDL 16.5) didn't seem to
catch it. It took the signal name USB0VBUS. Unfortunately, he had another
circuit
with USB_VBUS signal name that didn't get connected to this signal on the PCB.
Any ideas on why this wasn't checked? Thanks for any help!- DC
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