[PCB_FORUM] Cadence Design Entry HDL Checker
- From: "Carrow, Dennis" <dcarrow@xxxxxxxxxx>
- To: "'icu-pcb-forum@xxxxxxxxxxxxx'" <icu-pcb-forum@xxxxxxxxxxxxx>
- Date: Fri, 31 Aug 2012 18:56:07 +0000
My engineer accidently placed two signal names on the same net(see R1 below).
This seems like a basic error but Cadence(Design Entry HDL 16.5) didn't seem to
catch it. It took the signal name USB0VBUS. Unfortunately, he had another
circuit with USB_VBUS signal name that didn't get connected to this signal on
the PCB. Any ideas on why this wasn't checked? Thanks for any help!- DC
[cid:image001.png@01CD877F.5D5C9F80]
Other related posts:
