[ibis-quality] Proposed topic of discussion
- From: "David Banas" <david.banas@xxxxxxxxxx>
- To: <ibis-quality@xxxxxxxxxxxxx>
- Date: Mon, 28 Jan 2008 10:28:38 -0800
Hi all,
I would like to propose the following topic of discussion for one of our
meetings:
Are the Vinl/Vinh values given in the [Model] section of an IBIS model
supposed to represent the worst case input switching limits, over the
full range of legal operating conditions? That is, should:
* Vinl be the lowest value ever required at the input to switch
the gate low, and
* Vinh be the highest voltage ever required to switch the gate
high?
If so, then should it ever be allowed that the range of values given for
these two parameters in the [Model Spec] section extend below/above
these values, respectively? Currently, they do in both Micron and Xilinx
models, and I'm wondering if this is correct:
Xilinx
[Model] LVCMOS33_F_2
Model_type I/O
Polarity Non-Inverting
Enable Active-Low
Vinl = 0.76
Vinh = 2.2
Vmeas = 1.6500V
Cref = 0.0F
Rref = 1.0000M
Vref = 0.0V
C_comp 6.0000pF 6.0000pF 6.0000pF
[Model Spec]
Vinl 0.76 0.69 0.8
Vinh 2.2 2.0 2.3
Micron
[Model] DQ_FULL_667
Model_type I/O
|
Vinl = 700.000mV
Vinh = 1.100V
Vmeas = 900.000mV
Vref = 900.000mV
Cref = 0.0pF
Rref = 25.000Ohm
|
| typ min max
|
C_comp 2.830pF 2.400pF
3.250pF
|
[Model Spec]
| Input threshold voltage corners
Vinl 0.700V 0.650V
0.750V
Vinh 1.100V 1.050V
1.150V
Thanks,
David Banas, Sr. Staff Applications Engineer
Advanced Products Division
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