Hello David, from my point of view you are right. Vinl and vinh are worst case in datasheet. But that is why we (NSN ) are putting more realistic values in the models ( like the params from micron or xilinx ) First these parameters vinl and vinh are for the whole datasheet range ( normaly vcc +-10% ) The models we are using are at vcc +-5%. So if we would use datasheet parameters, we would do to much worst case simulations ( e.g. propagation delays from driver out to receiver in ( for a simple point-to-point connection ) would result in timing form driver to receiver: REC vinl 0.8V : 2.1ns REC vinh 2.0V : 2.8ns using more realistic params REC vinl 1.0V : 2.4ns REC vinh1.8V : 2.7ns so I will win 300ps / 100ps ) please see attached picture Mit freundlichen Grüßen / Best regards / Cordiali saluti / ystävällisin terveisin Eckhard Lenski Nokia Siemens Networks GmbH & Co. KG COO RA RD BTS HW GERAN BTS&NB&CP Dev SDE CAE libraries and models Balanstr. 59 81541 München Germany phone : +49 89 636 79002 fax : +49 89 636 78895 email: eckhard.lenski@xxxxxxx Nokia Siemens Networks GmbH & Co. KG Sitz der Gesellschaft: München / Registered office: Munich Registergericht: München / Commercial registry: Munich, HRA 88537 WEEE-Reg.-Nr.: DE 52984304 Persönlich haftende Gesellschafterin / General Partner: Nokia Siemens Networks Management GmbH Geschäftsleitung / Board of Directors: Lydia Sommer, Olaf Horsthemke Vorsitzender des Aufsichtsrats / Chairman of supervisory board: Lauri Kivinen Sitz der Gesellschaft: München / Registered office: Munich Registergericht: München / Commercial registry: Munich, HRB 163416 ________________________________ Von: ibis-quality-bounce@xxxxxxxxxxxxx [mailto:ibis-quality-bounce@xxxxxxxxxxxxx] Im Auftrag von ext David Banas Gesendet: Montag, 28. Januar 2008 19:29 An: ibis-quality@xxxxxxxxxxxxx Betreff: [ibis-quality] Proposed topic of discussion Hi all, I would like to propose the following topic of discussion for one of our meetings: Are the Vinl/Vinh values given in the [Model] section of an IBIS model supposed to represent the worst case input switching limits, over the full range of legal operating conditions? That is, should: * Vinl be the lowest value ever required at the input to switch the gate low, and * Vinh be the highest voltage ever required to switch the gate high? If so, then should it ever be allowed that the range of values given for these two parameters in the [Model Spec] section extend below/above these values, respectively? Currently, they do in both Micron and Xilinx models, and I'm wondering if this is correct: Xilinx [Model] LVCMOS33_F_2 Model_type I/O Polarity Non-Inverting Enable Active-Low Vinl = 0.76 Vinh = 2.2 Vmeas = 1.6500V Cref = 0.0F Rref = 1.0000M Vref = 0.0V C_comp 6.0000pF 6.0000pF 6.0000pF [Model Spec] Vinl 0.76 0.69 0.8 Vinh 2.2 2.0 2.3 Micron [Model] DQ_FULL_667 Model_type I/O | Vinl = 700.000mV Vinh = 1.100V Vmeas = 900.000mV Vref = 900.000mV Cref = 0.0pF Rref = 25.000Ohm | | typ min max | C_comp 2.830pF 2.400pF 3.250pF | [Model Spec] | Input threshold voltage corners Vinl 0.700V 0.650V 0.750V Vinh 1.100V 1.050V 1.150V Thanks, David Banas, Sr. Staff Applications Engineer Advanced Products Division