Dear all, I would like to bring up two questions about Arpad's module to today's meeting. 1) In IBIS_VCVS_ABS and IBIS_CCVS_ABS, voltages are defined as Scale*abs(V(in)) or Scale*abs(I(in)). So the derivative of function is not a smooth function but a step function, which might cause converge problem for analog simulator. It might be better to smooth those functions using slew filter in VerilogA. 2) In IBIS_VCVS_DIV and IBIS_CCVS_DIV, voltages are jump from some values to 1.0e+15 (for V(in2) or I(in2) equal to zero). This is another type of discontinuity which cause simulator converge issue. In my opinion, both cases might be general problems for all analog simulators. I'd like to hear comments from all of you. Thanks Shangli Wu