[ibis-macro] Updated VHDL-AMS macro model library posted

From: "Muranyi, Arpad" <arpad.muranyi@xxxxxxxxx>
To: <ibis-macro@xxxxxxxxxxxxx>
Date: Thu, 2 Feb 2006 14:13:27 -0800
Hello everyone,

A new revision of the VHDL-AMS macro model library has
been posted to our web site.

http://www.eda.org/pub/ibis/macromodel_wip/Macro_Lib_VHDL_SMASH_2006_02_01.zip

In this revision I added a FileRead function to make the
template level netlist nicer.  This way we don't have to
list all the parameters on the calling statement, only
the file name (from where these parameters are read by this
new function).  However, it is still possible to pass
parameters from the calling syntax too, in case someone
prefers that format.  Here is how it works:

If the file name is specified and the file contains the
parameter needed, that will be used.  If the calling
statement passes a parameter value in addition to the file
name, it will only use that value if the file does not
contain the same parameter.  If the file does have the
same parameter, the one in the file will be in effect.
If the file doesn't have the parameter needed (or no file
name is given), and the parameter is not passed in from
the calling statement, the internal defaults will be
used.  If a file name is given, but the file doesn't
exist, SMASH generates an error and stops.  (This may
be tool specific, because the way I coded it should
still continue using the internal defaults).

The other change I made in this revision is that I separated
out the commonly used functions, such as "FileRead", "Lookup",
"FindCommonLength", etc... into a separate file, so that they
would not have to be repeated in every single model that uses
them.  This file is called "MacroLib_functions.vhd" and sits
in the same directory as the "IBIS_macro_library.vhd" file.
This change has several advantages, which seemed to be more
important to me than keeping everything in a single file.
Please note that I did not do this with the Verilog-A(MS)
version of the library because due to the limitations of
the language that version does not use functions for the
above operations.  Although separation of repeated code may
be possible using include statements, it is quite risky to
do it that way due to variable naming and scoping reasons.

So this time I didn't do any changes to the Verilog-A(MS)
version of the library, so there is no posting on that one
today.

I am pretty happy with the state of the library now.  Aside
from the discussion of the possibilities of a few additional
features I consider this pretty much done.  Please take some
time and review it seriously, and ask questions if necessary
so we can make the changes before we solidify it for real.

I am now going to focus on writing the presentation for the
IBIS Summit in which I will give a technical overview of
the library with usage examples.

Arpad
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[ibis-macro] Updated VHDL-AMS macro model library posted

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