[ibis-macro] IBIS buffer implementation question

From: "Muranyi, Arpad" <arpad.muranyi@xxxxxxxxx>
To: <ibis-macro@xxxxxxxxxxxxx>
Date: Fri, 4 Nov 2005 12:39:36 -0800

Hello everyone,

This is hopefully an easy question.  Now that I started
working on the IBIS buffers for the VHDL-A(MS) version
of the library, I ran across this question.  I think
my work on the PWL sources made me aware of it...

What should be the threshold level(s) on the input stimulus
(and perhaps the enable also) to the buffer?  In the current
Verilog-A implementation I implemented a single value Vth
parameter with a default of 0.5V, however, I just remembered
that a very popular tool we all know does the following:

At t=0 for transient analysis (or for DC analysis), the
buffer goes to HIGH state if V_in > 0.5 and to LOW in the
opposite case.  Next, if the buffer is in HIGH state, it
will go to LOW state if V_in < 0.2.  If the buffer is in
LOW state, it goes to HIGH state if V_in > 0.8.

Another one of our very popular tools does it differently,
they go to the high state immediately when the input
value goes above 0V, and go to the low state immediately
when the input goes below 1V.

1)  Considering that in the event triggered PWL sources
I implemented two threshold parameters, Vth_R and Vth_F
for the rising and falling edge stimulus, the least I
think I should do is have two threshold parameters for
the buffer models also.

On the other hand, as far as I know, these favorite tools
of ours do not give an option to the user to change these
thresholds (but I could be wrong on that one).  If true,
wouldn't it be better if the library would also hard code
the threshold parameter?

2)  If the answer is hard code them, what should be the
value for Vth_R and Vth_F?  If the answer is don't hard
code them, what should be the default value for them?

Thanks,

Arpad
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[ibis-macro] IBIS buffer implementation question

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