We've been pondering several things over here in TeraspeedLand (sung to the tune of JungleLand, by Bruce Springsteen)
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Given a SerDes channel where:
* the Tx reference clock is based upon an external clock with it's
own unique stochastic properties
* the reference clock is then forwarded from the Tx to the Rx
* the Receiver uses the forwarded clock as the reference for a CDR
* there are both deterministic and random components to the clock
noise statistics
How would IBIS-AMI be used to model the impact of PLL jitter transfer,
amplification, and noise-injection, along with integrating that into
modeling and simulation of the PLL loop dynamic effect on DFE cascade
errors?
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Given a SerDes receiver where:
* the reference clock is derived from an external clock source with
it's own deterministic and random stochastic noise profile
*
* How would IBIS-AMI be used to model the impact of these noise
sources on the PLL loop dynamics, and their subsequent impact on
equalization and data recovery?
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Given compliance correlation studies on a serdes receiver:
* how can noise injected into the reference clock be modeled, along
with it's impact on equalization and data recovery?
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As you can see, I'm wondering how clock "stuff" fits into the flow.
regards,
Scott
--
Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax
http://www.teraspeed.com
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