[openbeos] Re: ARM port

> The biggest difference in the v7 stuff for os supporting is the  
> different cache architecture. ARM changed the cache control bits 
> again  
> for the cortex, and now it's somewhat more complicated, but it should  
> be documented if you have the arm v7 docs. Seeing as Nicholas works  
> for ARM he should be able to get ahold of it legitimately. Other than  
> that, it's for the most part just the same as v6. Thankfully the 
> cache  
> is now fully physically coherent, so none of that cache flushing mess  
> that you have to do on earlier arms, and some of the v6s.

I have the same problem with m68k, the 040 and 060 have different 
opcodes for cache invalidation stuff, I just used a function table as 
you can see in 
src/system/kernel/arch/m68k/arch_030_cpu.cpp

> Fully supporting thumb2 + neon + lazy fpu save is a bit more of a  
> challenge as well, since the kernel has to have enough knowledge to  
> decode the instructions and differentiate between a real bad  
> instruction and just a disabled fpu instruction.

Eh :)

> One area that haiku may bump into trouble is the general lack of  
> support for systems with dma incoherent devices. Most oses have some  
> sort of knowledge of this, and let you allocate regions with cache  
> disabled and whatnot to make it easier to sync with dma that happens  
> in the background. Without it you'll probably have to overly flush 
> the  
> cache in the low level drivers and there still may be some cache line  
> aliasing issues. Shouldn't be too bad, since most of the drivers 
> would  
> need to be custom to the board anyway.

hmm there is a B_DMA_IO flag in KernelExport.h.
And B_MTR_* flags...

François.

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