[SI-LIST] Re: source of DDR 4 timing recommendations
- From: Hermann Ruckerbauer <Hermann.Ruckerbauer@xxxxxxxxxxxxx>
- To: ericsilist@xxxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Sat, 02 Aug 2014 17:38:37 +0200
Hello Eric,
most of the design guides on DDRx memory use very strict requirements on
the lenght matching.
This comes from the fact that many people think this is an easy task and
comes for free. But I have seen several designs that have been length
matched to death.
Not sure where the 50mil and 90ps come from .. 1.25mm (50mil) are below
10ps so quite small, while 90ps is quite a bit for the given UI ..
I have seen the 1mm in several design guides and usually relax these to
5mm (~35 ps) .. at least for DDR3 this is usually acceptable, while I
would not give away the 90ps that you mentioned also ..
So you should make your own thoghts and check what is the real
requirement for your system.
But of course this means you have to understand the signaling to make
the right judgement.
DDR4 changes the concept a bit to DDR3 as it tries to work with BER with
some RX mask and tdiVW/VdiVW, what was not considered in DDR3.
And you will find numbers for the input valid window also in the JEDEC spec
just approaching this from a conventional point of view the high level
distribution of uncertainties is 1/3 for the TX (e. g. output
uncertainty for the controller), 1/3 fo the RX (e. g. DRAM setup/hold)
and 1/3 for the channel (e. g. ISI and X-talk effects). Building up a
timing budget will help you to understand what is allowed in your
simulation. ..
If some numbers are not in the JEDEC spec you should take your vendors
datasheet as source (I always look at both when working with DRAM
Memory). Some vendors will give quite a bit more data and explanation on
Valid window RX Mask and setup/hold times.
Regarding a good explanation on DRAM input timings: I think this is
difficult via e-mail and the reason why I do the DRAM seminar. So I
think you have to do a very thorough reading of the JEDEC and your
vendors spec in order to build up the understanding of the DDRx
signaling ..
Hermann
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Am 01.08.2014 21:49, schrieb eric silist:
> Can anyone help me understand the source of the pcb routing recommendations
> I see for DDR4. For instance DQ to DQS timing for a byte lane? I see
> some papers quoting 90ps or 50mil, but I don't know where those numbers
> come from.
> At a basic level I understand that DQS is the clock for the data byte on
> DQ, And that the total timing budget must be spread across chip, package,
> board, and dram. If I look at say DDR4-2800 that's a clock of 1.4Ghz with
> a period of 714ps. So at double data rate I figure each byte is 357ps
> wide. Then that should mean I have +/- 178ps of total margin that the DQS
> can move from it's ideal position of being in the center of the. I think
> :) Maybe that's where the 90ps for the board and 90ps for chip come from.
>
> Anyway I'm just having trouble finding a good explanation to help me
> understand how all that timing margin is calculated for each piece in the
> chain.
>
> I did try to look up DQ-DQS timing in the JEDEC standard and it just says
> TBD. I've found several docs that give me an idea of what values to use,
> but none so far that explain how they are calculated. I feel like this is
> still an SI related question since I'll use this information to setup
> constraints for my simulations but sorry if it's off topic.
>
> Thank you.
>
>
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