Balajy,
First, please keep in mind that target impedance is a rule of thumb the
impedance and is only one guide. The VRM itself can present large signal
responses, which are much larger than those predicted by impedance
assessment. Second, most specifications for the voltage are at the package
pins or balls and not the die, so you can generally end your assessment at
these connections to the device.
Next there are several different dynamic currents. At the very high
frequencies you can see the impact of the pin capacitance of the device and
this is often worse for small devices. For example a single UHS CMOS logic
gate can result in more than 50mA peak current with 300ps rise and fall
time. This is almost intolerance of inductance presented at the device.
This is also true for many transceivers and also memory devices.
Also, keep in mind that some devices, like the PLLs and clocks are much less
tolerance of noise and it isn't so much about keeping the voltage within
limits as it is about minimizing the impacts of noise on the jitter and even
microvolts of noise can be disruptive in these cases. This often means
managing the noise from switching of high speed devices, keeping it from
getting into sensitive devices.
Finally, keep in mind that these high speed currents that induce switching
noise are only one of many paths that cause power rail noise and you must be
careful in managing the other sources as well. For example crosstalk
between other rails and input source voltage transients can impact the rail
voltage as can turn on overshoot and switching induced ripple.
In the end, none of this is simple, and while we can use rules of thumb, use
them with caution and leave wide margins to account for all of these other,
less considered, aspects.
Steve Sandler
-----Original Message-----
From: FreeLists Mailing List Manager [mailto:ecartis@xxxxxxxxxxxxx] ;
Sent: Sunday, May 7, 2017 10:08 PM
To: si-list digest users <ecartis@xxxxxxxxxxxxx>
Subject: si-list Digest V17 #85
si-list Digest Sun, 07 May 2017 Volume: 17 Issue: 085
In This Issue:
#1: From: Binayak Shrestha <binayaks@xxxxxxxxx>
Subject: [SI-LIST] Re: Power Integrity - AC analysis
----------------------------------------------------------------------
Msg: #1 in digest
From: Binayak Shrestha <binayaks@xxxxxxxxx>
Date: Sun, 7 May 2017 11:54:14 +0530
Subject: [SI-LIST] Re: Power Integrity - AC analysis
Balajy,
It is not that straight forward.
While calculating the target impedance, I think we need to consider all the
current consumed by other devices feeding of that rail. How would you add up
the currents is a totally different story. It generally depends on the
frequency of the current drawn. This has been nicely explained by Larry
Smith (one of the guys who actually developed the target impedance concept)
in the following SI-List thread:
https://www.freelists.org/post/si-list/A-Question-about-Target-Impedance-Thr
eshold-computation,2
However, how much minimum impedance the power ground pads at the die can see
while looking outwards will depend on several factors like on-die
capacitance, on-die resistance, on-package capacitors, package lead
inductance, etc. These parameters will put a fundamental limit on how low
PCB board level impedance actually is effective.
Hope this helps.
Binayak
On Fri, May 5, 2017 at 3:50 PM, Balajy Kumar <BKumar4@xxxxxxxxxxxxxxx>
wrote:
Hi
I am doing Power AC analysis using hyper lynx tool. l am having doubt
in calculating the target impedance using transient current for Lumped
and distributed analysis.
Here I used 50% load current (sum of all the IC loads current in the
power
supply) to calculate Target impedance for lumped analysis since I
didn't find the transient current details.
I want to probe the impedance at one particular load point (IC) only
so I used distributed analysis to probe in one load IC in the power
supply. My question is which current I have to use to calculate the
Target impedance , 50% of sum of all the loads current or 50% of that
particular IC load current. Kindly clarify with details.
Also the frequency till which I need to validate the Target impedance
both in Lumped and distributed (one load IC)? Hope it will be clear.
Thanks
Balajy
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