[SI-LIST] Re: options for reducing EMI
- From: steve weir <weirsi@xxxxxxxxxx>
- To: "Chen, Sherman" <sherman.chen@xxxxxxx>, "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Wed, 03 Sep 2014 06:41:56 -0700
OK so your clock is leaking. Of the three measures: SSC is likely the
most effective thing you can control in software. SSC modulates at a
slow rate that should not bother any decently designed silicon.
If you can't buy enough margin w/ SSC, then physical issues: Stack-up,
shield bonding, stitch via distribution, crossing splits, cavity
resonances, etc will be things you will want to review.
Steve
On 9/3/2014 6:20 AM, Chen, Sherman wrote:
> Thanks, Steve.
> The freq. exceeding the EMI margin is 8GHz. Enabling SSC should help on that
> I think.
> Any impact & precaution for turning SSC on? Looks there would be no big issue
> since all our chip vendors claims their products work fairly well with SSC
> on...
>
> Best Regards,
>
> Sherman Chen
> Signal Integrity
> EMC Global Hardware Engineering
> Tel: +86 21 60951100-3329
>
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
> Behalf Of steve weir
> Sent: Tuesday, September 02, 2014 7:04 AM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: options for reducing EMI
>
> This is another infamous: "It depends".
>
> First: Will any combination of anticipated measures yield a solution that
> meets both your SI and EMC requirements?
> Second: Do you prioritize margin to SI or EMC, or split them?
>
> It sounds like you have a design that has failed EMC. Before twiddling
> anything that you can look at where you are failing and how badly.
>
> TX swing can only reduce noise in the best case dB for dB. So, if you just
> need a couple of dB to squeak by and have the link budget, it is an option.
> SSC can buy up to 10dB on the clock and harmonics.
> Edge rate could help if you have resonance issues. Otherwise, it is similar
> to fiddling with the Tx swing.
>
> Steve
> On 9/1/2014 1:43 PM, Chen, Sherman wrote:
>> Hi SI Gurus,
>> We are considering the following options in order to reduce the EMI of one
>> of our boards, which is mainly caused by the PCIe Gen3 link:
>>
>> 1. Reducing TX swing.
>>
>> 2. Turn on SSC.
>>
>> 3. Slowing down edge rate.
>> While we are running test to verify which option will bring us the best
>> result & least impact, any comments or suggestions from those who had
>> experiences on this matter?
>>
>> Best Regards,
>>
>> Sherman Chen
>> Signal Integrity
>> EMC Global Hardware Engineering
>> Tel: +86 21 60951100-3329
>>
>>
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>
> --
> Steve Weir
> IPBLOX, LLC
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--
Steve Weir
IPBLOX, LLC
1580 Grand Point Way
MS 34689
Reno, NV 89523-9998
www.ipblox.com
(775) 299-4236 Business
(866) 675-4630 Toll-free
(707) 780-1951 Fax
All contents Copyright (c)2013 IPBLOX, LLC. All Rights Reserved.
This e-mail may contain confidential material.
If you are not the intended recipient, please destroy all records
and notify the sender.
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