[SI-LIST] Re: design of on-chip PDN
- From: Cosmin Iorga <ci249534@xxxxxxxxx>
- To: Siming Pan <pansiming86@xxxxxxxxx>, Chris Cheng <Chris.Cheng@xxxxxxxx>
- Date: Tue, 2 Nov 2010 09:47:13 -0700 (PDT)
Siming,
For your question "How much impact for common impedance will the connection of
power net cause?" you can experiment various "what if" studies with a software
that I wrote, "ChipQuake Power Integrity Explorer", for which you can download
a
free version from the http://www.noisecoupling.com web site.
This software models the power distribution in a chip-package-PCB design having
two power supplies, one named analog and the other one digital (you may assign
them to match your design). The full version lets you define the power
distribution parameters for chip, package, and PCB and then simulate the noise
generated on the digital supply and the noise coupled into the analog supply.
The free version limits the functionality but you can still experiment with the
number of decoupling capacitors on the package and PCB.
Cosmin Iorga,
NoiseCoupling.com
http://www.noisecoupling.com
________________________________
From: Siming Pan <pansiming86@xxxxxxxxx>
To: Chris Cheng <Chris.Cheng@xxxxxxxx>
Cc: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
Sent: Mon, November 1, 2010 6:22:19 PM
Subject: [SI-LIST] Re: design of on-chip PDN
Hi All,
Thanks very much for your reply.
For the ASIC I am currently deal with, the voltage level for digital
serdes and core are the same. So the reduction of common impedance seems to
be the main reason that power nets for serdes and core are not connected.
However, since the on-chip decaps for core is 100 times larger than it for
digital serdes, common power net will significantly reduce SSN. How much
impact for common impedance will the connection of power net cause?
Regards,
Siming
2010/11/1 Chris Cheng <Chris.Cheng@xxxxxxxx>
> I've never dealt with an ASIC chip that doesn't have at least dual oxide to
> separate core and I/O power distribution. Unless you are in the low power
> business, there are many reasons why you want your I/O power higher than
> your core voltage with all the new small geometry processes.
> While common mode noise can be a concern, people have done tricks like on
> die regulators and play with PLL loop bandwidth to mitigate these problems.
>
> Chris Cheng
> Distinguished Technologist
> 3PAR- an HP Company
> HP StorageWorks Division
>
> www.hp.com
> www.3PAR.com
>
> PS Go Giants !!!!!!!
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of Siming Pan
> Sent: Monday, November 01, 2010 4:10 PM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] design of on-chip PDN
>
> Hi All,
> I have a basic question related to on-chip PDN design. Usually the supply
> voltages are designed to be isolated for core, SERDES
>
> digital, analog, termination, etc. This design may isolate the SSN
> couplings among each net. However, usually large on-chip decoupling
>
> capacitances are used for VDD core circuit. In the board design, we
> connect
> the power nets of VDD_core together with VDD_digitalã??
>
> Thus, switching noises generated from SERDES digital are suppressed by
> large
> on-chip decaps designed for core circuit. However,
>
> package inductances still play a bad role here to block the conducted path
> between noise source formed by digital circuit and core
>
> capacitances. Then why not use one common power net as the supply power for
> all the IC circuits, so that large on-chip decaps can be
>
> shared, if the voltage levels are the same?
>
> Regards,
>
> Siming Pan
>
>
> --
> Siming Pan
>
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--
Siming Pan
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