[SI-LIST] Re: ddr2 ansoft / EMC2 paper available for download

  • From: "Chris Cheng" <Chris.Cheng@xxxxxxxx>
  • To: "steve weir" <weirsi@xxxxxxxxxx>
  • Date: Sat, 3 Nov 2007 19:44:52 -0700

I have a simpler example.
What if the trace further from the edge of the PCB get via stitches right next 
to the trace instead of at edge. Do you think the EMI noise will be bigger or 
smaller than the case with trace closer to the edge but via stitch at the edge 
far from the trace ?
I would bet the close via case will always win.
I believe (if indeed the example is really signal/gnd/power/signal stackup) 
this is another classic example of what I have been saying "two wrongs don't 
make one right". 
If you start by denying the return current a direct path of return (i.e. one 
reference plane is ground and the other is power) you are asking for trouble 
and whatever remedy your through at it, be it thin core power/ground planes, 
crazy via stitches is just wasting your effort on a improper setup. 
Switch to ground reference plane for both and even with as small as one via 
near by will make it smaller than any thin core power planes or crazy via 
stitch you can throw at the wrong reference plane case.
For fear of sounding like a broken record, remember the two Chris Cheng rules 
of SI:
a) Manage your signal return 
b) Decouple your PCB power/ground up to 100MHz before hitting your package, 
manage the rest at the package and die level
 All the common SI/EMI problems start with violating my two rules. :-D
 
________________________________

From: steve weir [mailto:weirsi@xxxxxxxxxx]
Sent: Sat 11/3/2007 7:04 PM
To: Chris Cheng
Cc: si-list
Subject: Re: [SI-LIST] Re: ddr2 ansoft / EMC2 paper available for download



Chris, Jason can address the specifics of that signal path.  However in
general, it is important to note tat even a stitch via does not provide
a direct return path between the two planes of a cavity.  That is true
whether or not the two outer planes of the cavity are the same voltage
or not.  A stitch via, even one really close to a signal via provides a
reflection surface that redirects only some of the signal energy that
would otherwise expand further out through the cavity.

With this view it should be a little bit easier to intuit why the via
that was further from the PCB edge excited the cavity more than the one
near the edge even though the trace on that latter signal ran parallel
to the edge.  Being closer to stitch vias along the edge, that latter
transition saw a strong reflection boundary nearby and less total energy
went into the cavity laterally.

Best Regards,


Steve.


Chris Cheng wrote:
> Steve and Jason,
> Thanks for sharing.
> Let me clarify a question I have from the beginning.
> In page 21 of the presentation, it shows the signal transition consist of a 
> microstrip line switching from one reference plane on one side (ground) to 
> the opposite side (power). Is this really how the simulation and measurement 
> is done ?
> i.e. the image return current is denied a direct return path between the top 
> reference plane (ground) and bottom (power) ?
> Chris
> ________________________________
>
> From: si-list-bounce@xxxxxxxxxxxxx on behalf of steve weir
> Sent: Sat 11/3/2007 12:40 PM
> To: si-list
> Subject: [SI-LIST] Re: ddr2 ansoft / EMC2 paper available for download
>
>
>
> To all that asked to see Jason Pritchard of EMC2 and Ansoft's joint
> paper on via stitching and EMI it is available via anonymous ( quasi )
> on the ipblox FTP server:
>
> ftp.ipblox.com
> username:  anonymous@xxxxxxxxxx
> password:  anonymous
>
> It is located in the ftp://ftp.ipblox.com/Ansoft_first_pass_2007/ directory.
>
> regards,
>
>
> Steve
>
> --
> Steve Weir
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--
Steve Weir
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882

California office
(408) 884-3985 Business
(707) 780-1951 Fax

Main office
(401) 284-1827 Business
(401) 284-1840 Fax

Oregon office
(503) 430-1065 Business
(503) 430-1285 Fax

http://www.teraspeed.com <http://www.teraspeed.com/> 
This e-mail contains proprietary and confidential intellectual property of 
Teraspeed Consulting Group LLC
------------------------------------------------------------------------------------------------------
Teraspeed(R) is the registered service mark of Teraspeed Consulting Group LLC




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