[SI-LIST] Re: clock 48MHz simulation(one driver & two loads)
- From: steve weir <weirsp@xxxxxxxxxx>
- To: tseng.morgan@xxxxxxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Tue, 26 Oct 2004 10:38:37 -0700
Morgan, it sounds like you did not represent the loads properly in your
simulation. I would get that right before playing with the driver curves.
Steve.
At 03:18 PM 10/26/2004 +0000, acquking wrote:
>Hi all
>
>I do a clock 48MHz simulation(one driver & two loads) and have a
>correlation with simulation and measure result.The comparision
>performs a little time difference in rising and falling
>edge,especially falling edge.The difference is about 500ps in rising
>edge and 1ns in falling edge.(rising & falling time measue is
>between 0.8 and 2V,reciver spec is 1.2ns for maximum value).
>I think it due to spike poisition in edge is not a good match by
>simulation and measure result.IBIS is a behavior model that means
>one driver strength ability of clk generator is to one load to meet
>original design rule.Is there problem to perform 2 loads?Should V-I
>and V-t curve in this model be modified to meet 2 loads?
>
>Regards
>Morgan
>
>
>
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