[SI-LIST] Re: What does it means my Power Plane Impedance
- From: Rhaja3@xxxxxxxxxxx
- To: mahesh@xxxxxxxxxxxxxxx
- Date: Thu, 9 Sep 2010 04:07:03 +0000 (UTC)
Dear Mahesh:
Your 'Power Integrity' questions can be answered by buying the book; "Signal
and Power Integrity....SIMPLIFIED", 2ND EDITION by Eric Bogatin.
click on, or paste link below into your browser
http://www.amazon.com/Signal-Power-Integrity-Simplified-2nd/dp/0132349795/ref=tmm_hrd_title_0?ie=UTF8&qid=1284001137&sr=8-4
The book is excellent about explaining Signal and Power integrity, which
includes examples from scopes and simulations tools, while also providing
numerous mathematical formulas and approximations, (along with concepts of when
and 'when not' to use them).
The book promotes the concept of ideally, 'designing by using simulation tools'
(if possible), and if not, then by using the countless formulas and
approximations that are provided within the book.
It greatly helped me in answering many of the basic questions, and with helping
me see the bigger picture when designing for Signal and Power integrity, which
is:
QUESTION:
"What do the Signal and Power Integrity designs need to accomplish?"
ANSWER:
"That depends......."
EXPLANATION:
One should not blindly rely on the previous design 'scheme' that worked before.
Each project should be approached individually. One needs to design and build a
project not wholly based on componant data sheets, but instead by 'where' and
'how' the current project is intended to operate in 'THE REAL WORLD'.
No more, no less. Try not to 'over-design', and do not 'under-design'.
So when you ask; "...should a Power Plane impedance be equal to 'zero'?"...
The answer is; "That depends....does it NEED to be 'zero'?"
Will your project work just fine if the Power Plane 'target impedance' is 1
Ohm, 500 mOhms, 100 mOhms, or as close to 'zero' as you can afford?
"That depend" on many factors such as;
a) What is the projects highest operating frequency?
b) The overall "noise budget" for the project?
c) The overall power plane(s) Inductance?
d) The voltage(s) that the project is operating at?
e) What size, how many layers, and how thick do the layers need to be in the
projects multi-layer PCB, and between the Power/Gnd planes?
f) The amount of current required for the project?
g) How many devices/signals does the project require?
f) How many, and what type of bypass capacitors (and where to place them),
should be employed in the project to achieve the 'target-Impedance'?
There is not 'one perfect' or 'ideal' answer to your question, because the
'best answer' will depend on a individual projects overall design
specifications and constraints, (which will always change, at least to some
degree, from project to project).
The above mentioned book can assist you in discovering the answers to the
questions you have. (Make sure to get the 2nd edition, that edition includes
the power integrity sections)
If you don't want to pay for the book, ask your work to pay for it. (The book
is 'relatively' inexpensive, around $66 Dollars)
For someone starting out, it a great first book on the subject(s).
Good Luck.
Mark R.
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----- Original Message -----
From: mahesh@xxxxxxxxxxxxxxx
To: "Shahbaz Assad" <shahbaz_assad@xxxxxxxxxxx>, si-list@xxxxxxxxxxxxx
Sent: Wednesday, September 8, 2010 4:49:41 AM
Subject: [SI-LIST] Re: What does it means my Power Plane Impedance
Replies embedded below
At 01:56 PM 9/8/2010, Shahbaz Assad wrote:
>Hi Experts,
>
>What does it means by power plane impedance while doing Power
>Integrity analysis.
>
>The power plane impedance is kept at mili ohms for a wide range of
>frequencies for better PI.
>
>Kindly guide me
>
>1. what does it means by power plane impedance? The impedance seen
>by the IC Chip between the Vcc adn GND planes, to put it in a simple
>(but not exactly true) way.
>2. what should be its nominal value? As low as possible, ideally 0 ohms
>3. For better PI, should its value be as small as possible like
>2mOhms? Yes. Theoretically consider wires connected to the vcc and
>gnd pins of a chip which have 0 inductance and 0 resistance. That
>would be an ideal case with 0 power plane impedance. But
>unfortunately this never happens in real life.
>4. if yes? what is the reason. One issue in power plane is
>resonance. All conductors comprise R,L,c. With any RLC comes
>resonance frequencies. The impedance of circuits changes
>dramatically at resonance frequencies. For example an ideal C and L
>in series has zero impedance at resonance frequency and an ideal C
>and L in parallel has infinite impedance at resonance
>frequency. Effectively, at resonance frequency the power plane
>presents a high impedance to the chip so current will not flow in
>easily as needed at that frequency.
>
>
>Thanks In advance. I am new to SI and PI
>
>
>Thanks,
>Shahbaz Assad
>
>System design Engineer - WhizzSystems, Inc.
>
>_____________________________________
>Skypes ID: sassad85 |
>sassad@xxxxxxxxxxxxxxxx
>
>
>
>
>
>
>
>
>
>
>
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