[SI-LIST] Re: Terminating Resistors at PCB Edges
- From: Istvan Novak <istvan.novak@xxxxxxx>
- To: 'Mohamad Haghtalab' <mohaghtalab@xxxxxxxxx>
- Date: Thu, 03 Dec 2009 23:02:32 -0500
Hello Mohamad,
To specifically answer your question: you have to calculate the
equivalent impedance of the plane shapes
and place termination resistors evenly spread around the periphery such
that their cumulative resistance
matches the plane impedance. The equivalent impedance of the planes
(for a rectangular plane shape)
can be found for instance in Section 3, Mid-frequency-to-plane
interface, on page 7 of the manuscript
of "Distributed Matched Bypassing for Board-Level Power Distribution
Networks". You can get the file
at http://www.electrical-integrity.com/ >> Paper download.
As Brad pointed out, you dont want to connect the resistors across the
planes, they would draw too
much current. You need a series capacitor to each resistor. If the
layout is done properly to minimize
inductance, this is an effective way of suppressing the first few modal
resonances on medium and large
size planes.
Regards,
Istvan Novak
SUN Microsystems
Brad Brim wrote:
> hello Mohamad,
>
> Plane impedance is an AC concept [1]. Your question seems to imply you are
> considering terminating an AC phenomenon (parallel plate waves traveling
> between your planes) with resistors at the plane edges. However, don't
> forget these resistors also provide a DC path between planes. Even if you
> could choose the proper spacing and resistor value for AC parallel plate
> wave termination you would sink way too much DC current. Further, the
> parasitics of the mounting would make the effective impedance of each
> resistor frequency dependent and probably would not provide a broadband
> plane wave load.
>
> If your concern is plane resonances ... In other than a
> canonical/impractically-simple design, you're not going to eliminate plane
> resonances with resistors. You may wish to investigate decoupling capacitors
> between different power nets or stitching vias between planes of the same
> net. Keep in mind that decoupling capacitors form series RLC low impedance
> resonances looking into the power delivery network (PDN). Since the loop
> inductance from your observation point to the decap varies, each device can
> experience the RLC resonance at a different frequency. Using large-valued
> decaps is usually the first guess - assuming one will get a lot of charge to
> source switching currents. However, the RLC resonance behavior implies
> larger capacitances will be effective at lower frequencies (i.e.
> resonance=1/sqrt(L*C) rad/sec). You can guess at decap values and locations
> but there are also simulation tools available to verify how your PDN will
> behave. There are even simulation tools to optimize for maximum performance
> (low impedance Z(f), low noise V(t)) with lowest cost through automated
> selection of caps and locations.
>
> If your concern is plane emissions ... Some designers attempt to build a
> "Faraday cage" by placing decaps around the periphery of their planes. This
> attempts to minimize emissions by reducing plane edge voltage. It can help
> emissions (at least locally where you have capacitors) but it does not
> eliminate resonances - it only *changes* them. I've seen cases where adding
> caps locally with no other design changes has created (a) resonances with
> peaks in other locations to cause high emissions from those locations that
> previously had low emissions, (b) resonance-caused PDN impedance peaks at
> devices on the board that were not there previously. Again, simulation tools
> are available to predict board-level emissions and show you near field hot
> spots. Think of emissions computations as simply a postprocessing step after
> your SI/PI simulations, since the signal currents and plane-edge voltages
> are what cause emissions and these are available as part of your board-level
> SI/PI simulation. Without realistic sources for both signals and PDN (i.e. a
> SI/PI simulation) you won't have realistic sources to predict emissions -
> like having an antenna and not knowing the feed point or the signal; tough
> to predict the emissions.
>
> cheers,
> -Brad
>
>
> [1] Theoretically precisely, the lowest order parallel plate mode (the only
> one you are likely to encounter for PCBs and packages) is TEM and therefore
> has an impedance defined all the way to DC. You'll have issues coupling much
> energy into it at DC, but it is still present. The low frequency issues of
> concerned for the parallel plate mode is the enhanced coupling it implies
> amongst vias in your power delivery network.
>
>
>
>> -----Original Message-----
>> From: si-list-bounce@xxxxxxxxxxxxx
>> [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of steve weir
>> Sent: Thursday, December 03, 2009 4:40 AM
>> To: Mohamad Haghtalab
>> Cc: si-list@xxxxxxxxxxxxx
>> Subject: [SI-LIST] Re: Terminating Resistors at PCB Edges
>>
>> You can derive the edge impedance using Baudendistal. Istvan
>> Novak has published his calculation in various papers as well.
>>
>> Steve.
>> Mohamad Haghtalab wrote:
>>
>>> Hi all
>>>
>>> regarding the fact that currents flow in various directions
>>>
>> in a PCB Plane(power or ground)what's the value of plane
>> impedance ,we should consider e.g for using Terminating
>> Resistors at PCB Edges?,how can it be computed?
>>
>>>
>>> Thanks
>>>
>>> Regards
>>>
>>>
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