[SI-LIST] Signal integrity opening in 3PAR Inc
- From: Chris Cheng <Chris.Cheng@xxxxxxxx>
- To: "'si-list@xxxxxxxxxxxxx'" <si-list@xxxxxxxxxxxxx>
- Date: Wed, 3 Mar 2010 16:22:35 -0800
Senior signal integrity engineer
Primary responsibilities include the following:
* Generate PCB signal integrity routing rules and creat constrain files
* Perform post route design rules checks
* Develop electrical verification test (EVT) test plans and software
* Perform EVT on first system arrival
* Using 3D EM tools to generate PCB parasitics structures to understand
design trade offs
* Assist in SPICE analysis of ASIC DDR3 memory bus
* Assist in ASIC package design and generate package interconnect and SSO
models
JOB REQUIREMENTS
* BSEE required, MSEE preferred
* Knowledge of tools such as SPICE or Verilog-A/AMS , Matlab or Perl
scripts, CST MWS or HFSS 3D field solver
* Knowledge of Allegro PCB tool
* Knowledge lab testing equipments such as Oscilloscope, high speed probes
* Knowledge of Sigrity PowerSI tool
* Knowledge of Allegro Constrain manager
* 3+ years in hands on signal integrity analysis and testing
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