[SI-LIST] Re: Several questions
- From: "Ken Cantrell" <Ken.Cantrell@xxxxxxxxxxxxxxxx>
- To: "John Smith" <swagguy18@xxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Sun, 23 Jan 2011 11:26:41 -0700
John,
"CMOS VLSI Design: A Circuits and Systems Perspective", Neil H. E. Weste,
David Money Harris, 4th edition.
This is a sytems overview, and has the detail that you need while not going
too deeply into materials science. I'm sure there are many other texts that
cover this area.
1. The current through a MOS transistor is proportional to the (W/L) ratio
of the transistor, where W is the width of the diffusion, and L is the
length of the gate. Higher current(greater W/L ratio)equals greater speed.
Google "CMOS current" for formulas.
2. 45nm, 32nm nodes refer to:
"The International Technology Roadmap for Semiconductors refers to the
process node number to describe the half-pitch of a NAND or DRAM memory cell
extrapolated for a given year. Half-pitch being half the distance between
adjacent lines of memory cells. Of course some companies are more aggressive
and some are more conservative, so this number is only good in an average
timing sense."
A logic-based 45 nm process or 65 nm process has nothing to do with this
number. So it's an apples and oranges question since you are primarily
inquiring about general CMOS theory of operation.
Under the general theory of operation, for a 65 nm process for example, the
minimum feature size for the process, or minimum drawn channel length, is
50nm. A parameter called lambda is equal to 1/2 the minimum drawn channel
length (25nm), and the gate length is equal to 2* lambda(50nm). Once you
know the minimum gate length, you vary the diffusion width to get a desired
current level(4/2 lambda, 8/2 lambda, etc.). Why you do it this way, i.e.,
express things in terms of lambda, is explained in texts on the subject.
3. Google "resolution of oscilloscope".
4. An N type consumes less area than a P type due to the lower mobility of
the pMOS. One is not inherently stronger than the other. N types are used
for pulldown, P types are used for pullup. In a standard CMOS inverter,
they are balanced w.r.t. current draw so that trise and tfall are symmetric.
Regards,
Ken
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of John Smith
Sent: Saturday, January 22, 2011 7:29 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Several questions
Hi, experts,
I got a couple of confusing questions for you guys. I hope I could get some
advices from you. Thank you very much.
1. What determines the speed of a transistor?
2. When we talk about 45nm, 32nm node, what physical parameter of a CMOS are
we talking about? The width?
3. Data rate of an ossiliscope is given, how do we calculate the resolution?
4. N type and P type, which one is stronger?
Thanks.
John Smith
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