[SI-LIST] Re: SOC Limitation
- From: steve weir <weirsi@xxxxxxxxxx>
- To: Subramanya CK <Subramanya.CK@xxxxxxxxxxxxxxx>
- Date: Thu, 26 Jul 2007 21:13:17 -0700
CK a modern SOC has all those considerations. For any specifics and
trade-offs you need to take up capabilities with your foundry(s).
Steve
Subramanya CK wrote:
> Hi Steve,
>
> Thanks for the reply. I understand that the size of memory than can get
> into a chip depends on the foundry process technology. And if the chip is
> more memory centric we embed memories higher than 32MB into that chip.
> But I am interested in knowing are there any "other" factors (like Signal
> Integrity/Timing/Thermal ), which limit the number of memory cells into
> the SOC
>
> Best Regards,
> CK
>
> -----Original Message-----
> From: weirsi@xxxxxxxxxx [mailto:weirsi@xxxxxxxxxx]
> Sent: Friday, July 27, 2007 9:16 AM
> To: Subramanya CK
> Cc: si-list@xxxxxxxxxxxxx
> Subject: Re: [SI-LIST] SOC Limitation
>
> C K,
>
> Sorry, but I don't see any such quote in that reference. If it were there
> it would be wrong. How much memory can be embedded in a chip any given
> day increases with process technology just like anything else.
>
> Logic centric chips are structurally different from memory centric chips
> and this limits them to a lower memory density than the latter.
>
> Steve.
> Subramanya CK wrote:
>
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>> Hi,
>>
>> While going through an article on Dr. Johnson's web site
>> (http://www.sigcon.com/Pubs/news/2_15.htm) I read that even the most
>> advanced SOC (System on Chip) cannot embed more than 32 MB of memory.
>> Can someone please explain me what are the factors (silicon-level)
>> that limit embedding larger memories in SOC
>>
>> Best Regards,
>> Subramanya C K
>>
>>
>>
>>
>>
>>
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