It's always a question of how far you need to be pushing the limits, and the
PCB Stack-up. The voids underneath the signal Pins reduce reflections by
reducing capacitive dips in the impedance profile. The thinner the Dielectric
Layer underneath the Footprint, the higher is the propability that you may need
voids.
For signal speeds exceeding 4Gbps (and equivalent signal risetimes) I would
definitely recommend a 3D simulation to find the best solution. At lower
frequencies you can first check using a sinple trace impedance calculator. Add
the solder and pins to the PAD thickness and put in this number as the trace
geometry. Then play with the GND-plane distance to estimate if you need a void,
and if so, how big it should be.
BR
Gert
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-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On ;
Behalf Of David Banas
Sent: Friday, June 17, 2016 4:12 AM
To: SI-List
Subject: [SI-LIST] Request for advice, re: footprint design for Samtec QSH
connectors.
Hi all,
Would anyone care to offer an opinion on whether or not it’s a good idea to
excavate the ground plane metal beneath the pin lands of a Samtec QSH series
connector, when designing the footprint?
The example footprints on Samtec’s web site do NOT have this metal excavated,
but I’ve heard rumors that their SI team recommends this practice to those,
whom inquire. I’m just looking for some clarity and clarification on the
subject.
Thanks!
-db
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