[SI-LIST] Re: Relation between slew rate and ISI
- From: "Preethi Ramaswamy" <preethi.gowtham@xxxxxxxxx>
- To: "Curt McNamara" <CurtM@xxxxxxxxxxx>
- Date: Thu, 8 May 2008 08:48:51 -0700
I don't deny what you guys are saying. Wolfang, my simulations are totally
in sync with what you are saying.
Like I said, these simulation are to prove that we have to let go off this
technology of probing at any place other than at the receiver.
This is the first time I posted on this site and I must say I'm totally
impressed by the number of responses.
Thanks guys !
Preethi
On 5/8/08, Curt McNamara <CurtM@xxxxxxxxxxx> wrote:
>
> In your case this may not be a good plan. If the signal edge were perfect
> and the logic analyzer thresholds set exactly to your receiver it could be
> OK. However we have been talking about reflections which cause edge
> discontinuities. These could overlap either switching threshold or occur in
> the transition region between the defined Vih and Vil. Any of these
> situations could cause sampling errors.
>
>
>
> And as Wolgang has noted, the signal may be good at the receiver yet look
> bad in the line, or be bad at the receiver yet look good in the line.
>
>
>
>
> Curt
>
>
>
> Curt McNamara, P.E. // principal electrical engineer
> Logic Product Development
> 411 Washington Ave. N. Suite 400
> Minneapolis, MN 55401
> T // 612.436.5178
> F // 612.672.9489
> www.logicpd.com
> / / / / / / / / / / / / / / / / / / / / / / / / /
> This message (including any attachments) contains confidential information
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> If you are not the intended recipient, you should delete this message and
> are hereby notified that any disclosure, copying, or distribution of this
> message, or the taking of any action based on it, is strictly prohibited.
>
>
>
>
>
>
>
> *From:* Preethi Ramaswamy [mailto:preethi.gowtham@xxxxxxxxx]
> *Sent:* Wednesday, May 07, 2008 7:34 PM
> *To:* wolfgang.maichen@xxxxxxxxxxxx
> *Cc:* Curt McNamara; si-list@xxxxxxxxxxxxx; si-list-bounce@xxxxxxxxxxxxx
> *Subject:* Re: [SI-LIST] Re: Relation between slew rate and ISI
>
>
>
> Totally agree. From these simulations trying to prove that at higher speeds
> this kind of probing is not viable. Just need to clarify that, this is not
> scope probing, this is logic analyzer probing. So I really don't care much
> about how the signal looks. All I care is if the bit is sampled correctly as
> a 1 or a 0.
>
> On 5/7/08, *wolfgang.maichen@xxxxxxxxxxxx* <wolfgang.maichen@xxxxxxxxxxxx>
> wrote:
>
>
> Probing in the middle of the line can have its pitfalls when trying to make
> sense of the observed waveform (and relating those to the "true" waveforms
> seeing at the receive)r. One such issue arises when the receiver does not
> provide perfectly matched termination (i.e. receiver impedance different
> from line impedance, but also - which is always the case - when the receiver
> has some input capacitance). In this case - if your probe is further away
> from the receiver than a small fraction of a rise time - you will observe
> two distict partial partial transitions, while at the receiver you would see
> both lumped together at the same time (i.e. only a single transition).
>
> Extreme case as an example (easy to simulate e.g. in PSpice): 50 Ohm driver
> driving a 50 Ohm transmission line with a 1V step, receiver is completely
> unterminated (high impedance). The driver is thus launching a 500mV step
> into the line (voltage divider - 50 Ohm driver + 50 Ohm transmission line).
> The receiver will see a full 1V step (500mV incident + 500mV reflected),
> but a probe looking at the middle of the line will see a 500mV step, and
> then (one round-trip delay to the receiver and back later) as second 500mV
> step on top of it.
>
> Trouble is, if you are "somewhat" close to the receiver those two
> transitions may partially overlap and you may think the waveform fidelity is
> poor, when in reality all is fine at the receiver end.
>
> Wolfgang
>
>
>
>
> *"Preethi Ramaswamy" <preethi.gowtham@xxxxxxxxx>*
> Sent by: si-list-bounce@xxxxxxxxxxxxx
>
> 05/07/2008 04:12 PM
>
> To
>
> "Curt McNamara" <CurtM@xxxxxxxxxxx>
>
> cc
>
> si-list@xxxxxxxxxxxxx
>
> Subject
>
> [SI-LIST] Re: Relation between slew rate and ISI
>
>
>
>
>
>
> Hi Curt
> For my application, I'm trying to tap the signal to feed to a probe.
> The best point to place a probe is at the receiver but it isn't always
> possible.
> Hence, I'm trying out a few options, one of them being tapping the signal
> before the receiver.
> Preethi
>
> On 5/7/08, Curt McNamara <CurtM@xxxxxxxxxxx> wrote:
> >
> > This may have been covered already by Wolfgang's excellent responses:
> > The wave arrives at the load and any reflected energy is almost no prop
> > delay away.
> > In contrast, at other points on the line the reflected energy from the
> > load (or other discontinuity) arrives 2 x tpd later (where tpd is the
> delay
> > from the measurement point to the reflection).
> >
> > This is one reason we may not care about intermediate points on the line:
> > at the load we need to see signal quality and establish that there are no
> > voltage levels beyond our limits. At the source signal quality may not be
> as
> > critical, but checking voltage levels is important.
> >
> > Why would we care about intermediate points? They could affect crosstalk
> > or emissions. Any other perspectives on this?
> >
> > Curt
> >
> >
> > Curt McNamara, P.E. // principal electrical engineer
> > Logic Product Development
> > 411 Washington Ave. N. Suite 400
> > Minneapolis, MN 55401
> > T // 612.436.5178
> > F // 612.672.9489
> > www.logicpd.com
> > / / / / / / / / / / / / / / / / / / / / / / / / /
> > This message (including any attachments) contains confidential
> information
> > intended for a specific individual and purpose, and is protected by law.
> If
> > you are not the intended recipient, you should delete this message and
> are
> > hereby notified that any disclosure, copying, or distribution of this
> > message, or the taking of any action based on it, is strictly prohibited.
> >
> >
> >
> > -----Original Message-----
> > From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
> > On Behalf Of Preethi Ramaswamy
> > Sent: Tuesday, May 06, 2008 5:52 PM
> > To: si-list@xxxxxxxxxxxxx
> > Subject: [SI-LIST] Relation between slew rate and ISI
> >
> > I'm looking for some information on the relation between slew rate and
> ISI
> > effect on high speed memory data signals.
> > From my SI simulation I'm observing that a signal looks much worse with a
> > higher slew rate than a lower slew rate. But the point I'm tapping is not
> > at
> > the receiver but a point before the receiver. I don't expect the signal
> to
> > look as good as at the receiver but I was hoping that the trends match.
> At
> > the receiver itself, the fast corner signal looks better than the slow
> > corner signal. The bus is properly terminated.
> > Looking at the waveform, I see that in the fast corner case, whenever
> > there
> > is a 1010 pattern, the signal is not reaching its intended Vhigh and Vlow
> > level. A similar thing happens at the slow corner but the signal swing is
> > much better. Hence, the eye diagram in the fast corner is almost closed
> > whereas the slow corner looks open.
> >
> > While searching some artciles on this, I found the opposite stated. It
> > said
> > that ISI effects are more pronounced in the slow corner case and
> Crosstalk
> > is more pronounced in the fast corner case.
> >
> > Any experience or insight into this topic would be very helpful.
> >
> >
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