[SI-LIST] Re: Mysterious "glitch" in the simulation?
- From: steve weir <weirsi@xxxxxxxxxx>
- To: Cuong Nguyen <cuong@xxxxxxxxxxxxx>
- Date: Tue, 26 Jul 2011 16:56:00 -0700
Cuong, you are getting a negative reflection from the Z mismatch caused
by the pin capacitance. As Dan said, it is an artifact of not being at
the end of the line and is nothing to worry about.
Steve
On 7/26/2011 4:38 PM, Cuong Nguyen wrote:
> Scope photo:
>
> http://imageshack.us/photo/my-images/34/tmp1n.jpg/
>
> Circuit topology:
>
> http://imageshack.us/photo/my-images/197/tmp22n.jpg/
>
> Measurements were made at the receiver end at the pin. Measurements at the
> die (not shown)
> do not show the glitch.
>
> Cuong
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
> Behalf Of steve weir
> Sent: Tuesday, July 26, 2011 4:13 PM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: Mysterious "glitch" in the simulation?
>
> The SI-LIST server strips attachments. Post your pictures to something
> like imageshack and include a link.
>
> What is the topology from the driver to the receiver? Where are you
> measuring in your simulation?
>
> A double inflection such as a glitch implies L/C or Tx line reflection.
> That the series termination does not seem to affect the glitch much
> implies that the oscillation occurs between the driver and the
> transmission line. Excessive package inductance and/or capacitance for
> the driver's edge rate and strength could do such things to you.
>
>
>
> Steve.
> On 7/26/2011 3:48 PM, Cuong Nguyen wrote:
>> Content-Type: text/plain;
>> charset="us-ascii"
>> Content-Transfer-Encoding: 7bit
>> Colleagues,
>>
>>
>>
>> I'm seeing a small "glitch" in a relatively simple simulation and would
> like
>> to solicit your expert observations.
>>
>> Instead of showing 2 circuits and 2 scope traces I'm showing one set only
>> but will try to explain.
>>
>>
>>
>> 1. The original circuit does NOT have the series R1 resistor (17-ohm
>> suggested by the wizard)
>>
>> 2. The scope trace shows the result of the original circuit.
>>
>>
>>
>> My observations:
>>
>>
>>
>> 1. The "glitch" stays in both cases (with or without the series
>> termination)
>>
>> 2. With termination, the upper value of the voltage output is
> reduced
>> and the lower value
>>
>> is increased a little. The general shapes are the same in both cases.
>> However, because
>>
>> the "glitch" is shifted down (with termination) this now crosses the
>> threshold area and becomes
>>
>> problematic.
>>
>>
>>
>> The questions are:
>>
>>
>>
>> 1. What is this glitch? Is it from the package model? (If I choose
>> die I do not see the glitch)
>>
>> 2. What might be some ways to resolve this? (Or, is this some
>> simulation artifact?)
>>
>>
>>
>> Thanks for your inputs
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>> === === === === === ===
>>
>> Cuong Nguyen
>>
>> Field Application Engineer
>>
>> EDA Direct Inc
>>
>>
>>
>>
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>
--
Steve Weir
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