[SI-LIST] MGB/s pair crossing on adajent layers
- From: Hirshtal Itzhak <ihirshtal@xxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Wed, 02 Jun 2010 13:37:15 +0200
Hi Experts!
I use double-stripline layers for MGb (PCI-Ex, sRIO) pair routing. I
ordered the PCB Designer not to route such pairs on adjacent layers,
close to each other, not even PERPENDICULAR to each other.
Now it seems I can't avoid it any more. My PCB Designer seems to run out
of real-estate.
I have 4-mil separation between the 2 layers and 4-mil from each one to
a GND layer on each side.
The pairs are running at 2.5 to 3.125 Gb/s
What risks, if any, I run into, if I do permit routing the pairs
perpendicular to each other? Are there any precautions I should take
while doing it?
Thanks
Itzhak Hirshtal
Elta
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