[SI-LIST] Load capacitance on Address pin

From: ravi <ravi@xxxxxxxxxxxxx>
To: si-list@xxxxxxxxxxxxx
Date: Fri, 19 Mar 2004 11:58:07 +0530

Hi All;
I need to connect the 100MHz address bus to memory and several other
peripherals. My processor data sheet specifies the address pin load/drv
capacitance as 50pF. Now assuming a load capacitance of x pF at each of
the peripheral chip pins what is the maximum number of Address input
pins to which this signal can be connected un-buffered. Apart from the
pin capacitance and the trace capacitance of  say 'y' pF are there any
considerations? Or is it just enough to add up the pin capacitances and
equivalent trace capacitances and keep it within the 50pF specification.

Secondly, which is the best routing topology to ensure maximum
un-buffered loading.

Thanks;
Ravi

------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field

or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list

For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field

List FAQ wiki page is located at:
                http://si-list.org/wiki/wiki.pl

List technical documents are available at:
                http://www.si-list.org

List archives are viewable at:     
                //www.freelists.org/archives/si-list
or at our remote archives:
                http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
                http://www.qsl.net/wb6tpu

[SI-LIST] Load capacitance on Address pin

Other related posts: