[SI-LIST] Job opening, Freescale India.

From: Ajay G <ajay.pisi@xxxxxxxxx>
To: si-list <si-list@xxxxxxxxxxxxx>
Date: Mon, 1 Aug 2011 13:46:59 +0530
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*Package Signal Integrity Power Integrity (PISI) Design Engineer:*
  *Department Description *



World Wide Design.







*Job Location *
  Noida, India






*Scope of Responsibilities/Expectations *



- Develop and drive Package Design activities in Networking group of
Freescale.

- Drive Flip Chip Package designs for High Performance SOCs.

- Drive Wire Bond Package designs for Cost sensitive SOCs.

- Package Signal Integrity and Power Integrity Analysis..

- Package model generation ? S-parameter models, Broadband spice models, RLC
models

- Package Model Extraction with 2D and 3D field solvers.

- IBIS model generation and support to customers.

-System level Signal Integrity Simulation

- Package simulations for parallel bus interfaces like DDR

- Package simulations for serial interfaces like PCIe, SATA, SRIO etc.

-Drive common package simulation methodology across business groups.

-Participate in Board system level and Test debug investigations to drive
root-cause understanding.

- Passion for driving processes and enhancing customer experience













*Specific Knowledge/Skills *



  - Basic Knowledge of SERDES, DDR, CMOS I/O designs with emphasis on how to
design Package and boards around them.

- Basic Knowledge about Board Design or Package Design process.

- Power Distribution Network understanding at the chip and system level.

- Understanding of different tools needed for design and simulation of
packages.





If you are looking for change please, forward your CV to me at
ajay.pisi@xxxxxxxxx or ajay.gaite@xxxxxxxxxxxxx


Thanks
Ajay

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[SI-LIST] Job opening, Freescale India.

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