[SI-LIST] Implementing high speed DDR3 memory interfaces webcast
- From: "Salman Jiva" <sjiva@xxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Thu, 29 Nov 2007 17:08:22 -0800
Implementing high speed DDR3 memory interfaces webcast.
This is on-demand so you can view anytime.
http://www.accelacomm.com/jlp/silist/0/80233551/
With today's requirements for high-speed memory interfaces surpassing 1
Gbps, FPGA silicon and IP must be designed to provide robust signal
integrity and address the challenges of implementing DDR3 interfaces.
Simulation still plays an important role in validating signal levels and
timing margins.
This webcast will discuss the challenges of implementing DDR3, and
available solutions.
At this webcast, you'll learn:
* The JEDEC requirements for DDR3
* How to address read/write leveling in your system
* How to reduce power consumption on your board and track PVT
Enjoy
Salman
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