Hi Nick I agree with Patrick Carrier 1. Make sure you are looking at the receiver (I have simulated this and have a hard time getting any non-monotonic waveform at the reciever when the driver is LVCMOS capable of 24 ma drive using stripline or microstrip at 50 ohms) (increase the R to 50 ohms but I believe the risetime of your driver must be very fast) 2. Make sure your IBIS model for the driver is good Steven salkow Lockheed -----Original Message----- From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of Carrier, Patrick Sent: Thursday, January 14, 2010 10:33 AM To: Lockard, Nickolaus J.; si-list@xxxxxxxxxxxxx Subject: [SI-LIST] Re: How to improve non monotonic Hi Nick-- Usually, termination works best. In the case you describe below, with your series termination, it sounds like you should have nice clean edges. Some ideas as to why you might be seeing the glitch: If this is in a simulation: 1. Make sure you are looking at the receiver signal 2. Make sure your IBIS model waveforms for the driver look good 3. Make sure you are using an LVCMOS or similar input impedance receiver Or if this is a lab measurement: 1. Make sure you are looking at the receiver signal 2. When measuring, make sure you are using a high bandwidth, high-impedance probe, that is connected close to the receiver without any large wires on the signal probe or the reference connection 3. If you are doing all that, this glitch could also be crosstalk or ground bounce, so you may want to look into that as well --Pat Patrick Carrier Technical Marketing Engineer High Speed Design Mentor Graphics Corporation Patrick_Carrier@xxxxxxxxxx ph. (512) 425-3015 -----Original Message----- From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of Lockard, Nickolaus J. Sent: Thursday, January 14, 2010 12:00 PM To: si-list@xxxxxxxxxxxxx Subject: [SI-LIST] How to improve non monotonic Hello, In general, how can one improve the quality of an LVCMOS clock signal that has a non-monotonic trailing edge? The circuit is an LVCMOS driver, 25MHz, 3.3V, with a series 33.2 ohm resistor at the driver, 50 ohm trace, 4 inches. The problem is the trailing edge of the clock starts to rise back up and approach the allowable threshold before it begins to fall back to 0V. How can this rise be dampened, or eliminated? Thanks, NL ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List technical documents are available at: http://www.si-list.net List archives are viewable at: //www.freelists.org/archives/si-list Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List technical documents are available at: http://www.si-list.net List archives are viewable at: //www.freelists.org/archives/si-list Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List technical documents are available at: http://www.si-list.net List archives are viewable at: //www.freelists.org/archives/si-list Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu