[SI-LIST] How to create a simulation model for a MCM DEVICE by building a test PCB.

  • From: Bernadine Splettstoeszer <bernadineps@xxxxxxxx>
  • To: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
  • Date: Wed, 26 Oct 2011 16:13:06 -0500

Good afternoon SI gurus,

I have a MCM device that has no models and am wanting to create a test PCB with 
the purpose of extracting lab data to then create models for it.  The Hyperlynx 
tool has an application that allows one to create custom IC Models called .MOD 
Models.

There could be 2 goals for this effort,
1. Modeling the I/O @ the MCM 
   MCM IO Drivers tested with a 50ohm trace into a 50ohm PD and a 50ohm PU 
using the voltage divider equation for the output high & low impedance.

  MCM IO RECEIVERS. 
   I AM UNSURE OF HOW TO TEST FOR THE MCM RECEIVER IO FOR THE PURPOSE OF 
CREATING A SIMULATION MODEL FROM LAB DATA???  
Probably get an FPGA to drive to the MCM receiver thru a 50ohm trace...not sure 
how to characterize the input resistance - measure current thru a 50 ohm series 
resistor as well as voltage to come up with the Input resistance.....I could 
play with the clamp diode settings in the Hyperlynx tool until I saw a similar 
OS/US conditions when compared to the scope data....??
2.  Modeling the IO at the die bond wire (not sure I have access but will 
assume for now - maybe :) )
   Going out on a limb here since I have never probed a signal at the bond wire 
(I imagine very fragile work if even possible)
The goal would be the same as above except the combination of MCM data from #1 
- #2 = what I would define as the parasitics not including the IC die.

Sent from my Windows Phone
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