[SI-LIST] Re: How to connect Chassis ground to DGND
- From: "Lee Ritchey" <leeritchey@xxxxxxxxxxxxx>
- To: "Chris Padilla" <cpad@xxxxxxxxx>, si-list@xxxxxxxxxxxxx
- Date: Wed, 3 Mar 2004 08:39:34 -0800
Chris,
The last two sentences weren't truncated. The reason to avoid tying logic
ground to the Faraday cage in more than one place is to avoid providing a
secondary path for current that should flow in the ground planes of the
system, namely the skin of the Faraday cage. A common symptom that this
has happened is that EMI seems to leak out of the box at the cracks.
I am aware that many companies, including Cisco, tie logic ground to card
guides and face plates. They often have a difficult time making the box
pass EMI as a result.
You don't need to tie logic ground to the case many places to control ESD.
ESD is a relatively low frequency event that can be controlled with a band
of copper around the edge of the outer layers of a PCB that is tied back to
the backplane only.
Hope this helps.
Lee
> [Original Message]
> From: Chris Padilla <cpad@xxxxxxxxx>
> To: <si-list@xxxxxxxxxxxxx>
> Date: 3/1/2004 4:56:29 PM
> Subject: [SI-LIST] Re: How to connect Chassis ground to DGND
>
> At 01:54 PM 2/29/2004 -0800, Lee Ritchey wrote:
> >I've watched this one from a distance. I'm not sure what the objective
of
> >tying logic ground to "chassis" ground. There are at least tow possible
> >reasons.
> >
> >1. To meet the UL safety specification.
> >
> >2. To help control EMI.
> >
> >In the first case, logic ground doesn't need to be attached to the
chassis
> >ground to do this. The chassis needs to have a good connection to the
> >green wire that goes back to earth in the AC system,
> >
> >In the second case, using the word chassis when discussing EMI confuses
> >things. In this case, the product is surrounded by a Faraday cage, which
> >likely has parts of the chassis as sides. If this is the situation, it
is
> >important to make sure currents that belong in the logic ground system
> >don't have an opportunity to flow in the Faraday cage. This can happen
if
> >logic ground is tied to the Faraday cage in more than one place.
Symptoms
> >of this happening are the complaint that EMI is "leaking" at the cracks.
A
> >common error is to tie the backplane logic ground to the Faraday cage
> >around its periphery (Good Idea) to form one side of the Faraday cage.
> >Then, the faceplates of the PCBs or their edges are also tied to the
> >Faraday cage. (Not a good idea)
>
> Lee,
>
> I'm curious about the the last two sentences above...I hope my truncation
> of the message doesn't hurt the intended context....
>
> You say a "common error" is to tie the BP periphery to the cage to form
one
> side of the Faraday cage but then say it is a good idea. I'm confused
here.
>
> The last sentence states that it is a bad idea to tie the PCB board edges
> and faceplate (presumably on a carrier tray) to the chassis or Faraday
> cage. Why is that? We often do this to protect against ESD but I must
> confess that I haven't tested any of my boards in a situation where the
PCB
> edges or carrier tray (faceplate) haven't been attached to the Faraday
cage.
>
> Thanks,
>
> Chris Padilla
> EMC Engineer
> Cisco Systems
>
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