[SI-LIST] Re: High Speed Design Class in Boston Area, October 18 & 19
- From: "Lee Ritchey" <leeritchey@xxxxxxxxxxxxx>
- To: "Hassan O. Ali" <hassan@xxxxxxxx>, r_shirsat@xxxxxxxxxxx
- Date: Thu, 16 Sep 2004 08:51:14 -0700
Many of you have attended the High Speed PCB and System Design class
conducted by Lee Ritchey of Speeding Edge.
Perhaps you have a colleague who you think would benefit from attending.
There is still some space in the class.
You can enroll by logging onto www.speedingedge.com
Lee W. Ritchey
Speeding Edge
P. O. Box 2194
Glen Ellen, CA 95442
Phone- 707-568-3983
FAX- 707-568-3504
I just used the energy it took to be angry to write some blues.
Count Basie
> [Original Message]
> From: Hassan O. Ali <hassan@xxxxxxxx>
> To: <r_shirsat@xxxxxxxxxxx>
> Cc: <si-list@xxxxxxxxxxxxx>
> Date: 9/16/2004 7:59:16 AM
> Subject: [SI-LIST] Re: Open/Short Circuit Impedance of the board
>
>
> Assume the network in question is made up of one series inductance
element followed by
> one shunt capacitance element (closer to the load). Now, if the load is
short-circuited,
> the whole network will be represented by the series inductance element.
That is, the
> input impedance Zsc = jwL (the impedance of the series inductance
element). When the
> load is open-circuited, the network will actually be represented by the
inductance
> element in SERIES with the capacitance element. That is, the input
impedance Zoc = jwL +
> 1/jwC. If Zsc and Zoc are known, L and C can be computed.
>
>
> In most high-speed applications, however, the networks are distributed.
That is, the
> network is actually a connection of a multitude of the above-described LC
networks. If
> an entire distributed network is represented by one LC network, then the
"L" is,
> strictly speaking, the "effective inductance" and the "C" is the
"effective capacitance".
>
> When you have conduction and and dielectric losses, then the series
resitance (R) and
> shunt conductance (G) will also come into the equations.
>
> Hope that helps.
>
> Hassan.
>
>
> On Sep 16, "Craig Clewell" <cclewell@xxxxxxxxx> wrote:
> >
> > Rohan,
> >
> > Without knowing anything else about what you are reading it sounds like
> > they are referring to the capacitance and inductance. If you were to
> > short the end of the line and measure you get the inductance, and if you
> > open the end of the line you get the capacitance. These values can be
> > read from the smith chart at low frequencies by looking at the S11
> > measurement provided that the line is shorter than lambda/4.
> >
> > Craig
> >
> > -----Original Message-----
> > From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
> > On Behalf Of Rohan Shirsat
> > Sent: Thursday, September 16, 2004 5:26 AM
> > To: si-list@xxxxxxxxxxxxx
> > Subject: [SI-LIST] Open/Short Circuit Impedance of the board
> >
> >
> > Hi All,
> >
> > I was going thru Sigrity tutorial and there was a section on Open/Short
> > Circuit Impedance of the board. Can some1 explain in brief what that
> > means.
> >
> > Cheers
> > Rohan R Shirsat
> > Intel Corp
> > ICPE CDTG Power Delivery
> >
> > +91-80-25075861
> > rohan.r.shirsat@xxxxxxxxx[1]
> >
>
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