At 10GB/s you generally need to do some sort of modeling and simulation of
your channel. I don't think you will get all the answers on this forum
because there are a lot of "It Depends" caveats.
That being said, to answer your questions on vias, yes via anti-pads are
important at these speeds since they will affect the via impedance. By
definition, anti-pads are the clearance holes in the plane layers to allow
the via to pass through without shorting out. So you cannot eliminate
anti-pads. Too small of an anti-pad usually manifests itself into higher
excess via capacitance, lowering the via impedance, while too large makes
the via look too inductive raising the impedance. You need to model the via
geometry to get the answers you need. You can do quick what-if scenarios to
see the effect of anti-pads on via impedance by referencing one of my blog
articles here:
https://blog.lamsimenterprises.com/2011/03/14/the-poor-mans-pcb-via-modeling
-methodology/
While you are there, there are other articles on vias you might find useful.
There are also commercial software tools, like Hyperlynx, Simbeor and Ansys,
for example, that can be used to take it to the next level once you narrow
down suitable candidates.
With regards to your question on via stubs, it is the 1/4-wave resonance
frequency of the stub that can kill your signal if it lines up at or near
the Nyquist frequency of the bit rate. Usually thick boards with long stubs
are an issue, and I am not aware of any receive equalizer that will
compensate for that.
Regards,
Bert Simonovich
Signal/Power Integrity Practitioner | Backplane Specialist | Founder
LAMSIM Enterprises Inc.
Innovative Signal Integrity and Backplane Solutions
Web Site: http://lamsimenterprises.com/ ;
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Carson Au
Sent: 3-Nov-16 4:20 PM
To: John
Cc: Lee Ritchey; Loyer, Jeff; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: HDI and SERDES Channels
For example, let's just say some pedestrian 10Gb/s channels.
Are layer-transition via anti-pads important at those speeds? Can I
generally eliminate anti-pads for these channels to gain better routing
density?
If via stubs manifest themselves as losses on the channel, can I not care
about these stubs because now the SERDES receiver can recover from extreme
losses in the channel?
On Fri, Nov 4, 2016 at 7:10 AM, John <johndp@xxxxxxxx> wrote:
What is and what isn't important in your design is largely dependant
on the speed you want to go. So giving the list an indication of the
operating bit rate of your Serdes will enable us to better answer your
question
Regards
John
Sent from my Sony Xperia⢠smartphone
---- Carson Au wrote ----
If loss isn't usually the problem, does that mean usually smooth
copper usually doesn't have to be considered in the design (or are
there more benefits to smooth copper than just lower loss?) Lee, what
are the top problems in modern SERDES layout in your opinion (besides
the fibre weave effect)?
On Fri, Nov 4, 2016 at 3:21 AM, Lee Ritchey <leeritchey@xxxxxxxxxxxxx>
wrote:
Before I would do any of that, I would do some analysis to see whatthis
the losses would be if normal striplines are used. My experience is
that
extra work would not be necessary.but
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]
On
Behalf Of Loyer, Jeff (Redacted sender "jwloyer" for DMARC)
Sent: Thursday, November 3, 2016 8:16 AM
To: carson.au@xxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: HDI and SERDES Channels
I think you'd have to void the layers above or below your signal traces.
For instance, I can imagine routing the longest lengths on the
outermost layers of the "core" of a build-up stackup and voiding
layers above those traces to allow me to widen the traces (they
would also be relatively thick, further lowering loss). You'd want
a solid plane above them somewhere,
it doesn't have to be the adjacent layer. You'd also have to beto
careful
specify smooth copper on those layers, else the manufacturer willprobably
undo your great efforts by putting rough copper on them.control
Jeff
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]
On
Behalf Of Carson Au
Sent: Thursday, November 03, 2016 5:07 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] HDI and SERDES Channels
Hi Experts,
From my understanding, HDI build-up layers require thin prepreg
layers, leading to very thin trace widths for 100ohm differential
impedance
- and your high speed serial links would suffer great conductor loss.either
How do you mitigate against this?
If your design has many build-up layers with thin build-up layers on
side of your stripline, then it is impossible to even get something
like 100um (4mil) trace widths for your 100 ohm differential pairs!!
Regards,
Carson
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