[SI-LIST] Re: HBA PCIe gen2 test w/o using CBB
- From: "Chen, Sherman" <sherman.chen@xxxxxxx>
- To: Nathan JP <jpnathan@xxxxxxxxxxx>, "'si-list@xxxxxxxxxxxxx'" <si-list@xxxxxxxxxxxxx>
- Date: Fri, 4 Jul 2014 08:21:35 +0000
Hi Nathan,
Yes, AIC RX is what I referred to.
The reason to probe at connector rather at BGA is the via under BGA is coated.
Thanks for the help.
Sherman Chen
Signal Integrity
EMC Global Hardware Engineering
Tel: +86 21 60951100ext3329
From: Nathan JP [mailto:jpnathan@xxxxxxxxxxx]
Sent: Thursday, July 03, 2014 6:19 AM
To: Chen, Sherman; 'si-list@xxxxxxxxxxxxx'
Subject: RE: [SI-LIST] Re: HBA PCIe gen2 test w/o using CBB
Hi Sherman,
By HBA Rx, do you mean the Rx channel in the Add-in card (which
connects to Sys Tx)?
For Rx qualification, there are separate Tolerance/Sensitivity tests Spec.
(If the Rx pins are accessible, then the end-to-end measurements can be made at
both the Rx to verify full-channel sig quality w.r.t. 2.0 Rx Base spec limits).
Regards,
Nathan JP
> From: sherman.chen@xxxxxxx<mailto:sherman.chen@xxxxxxx>
> To: jpnathan@xxxxxxxxxxx<mailto:jpnathan@xxxxxxxxxxx>;
> si-list@xxxxxxxxxxxxx<mailto:si-list@xxxxxxxxxxxxx>
> Subject: [SI-LIST] Re: HBA PCIe gen2 test w/o using CBB
> Date: Wed, 2 Jul 2014 20:19:28 +0000
>
> The mail got scrambled resent w/ plain text.
> Best regards,
>
> Sherman Chen
> Signal Integrity
> EMC Global Hardware Engineering
> Tel: +86 21 60951100ext3329
>
> From: Chen, Sherman
> Sent: Wednesday, July 02, 2014 5:08 AM
> To: 'Nathan JP'; 'si-list@xxxxxxxxxxxxx'
> Subject: RE: [SI-LIST] HBA PCIe gen2 test w/o using CBB
>
> Hi Nathan,
>
> Thanks. we are using common clock configuration even so we still need to
> rely on the ext. clock if measuring the jitter using scope-only method (no
> SigTest). I mean the constant clock provided by the scope.
> Although what we are designing is HBA card, it may still be necessary to run
> the test for SYS TX, ie, HBA RX, to verify the signals is all right at the
> PCIe connector. Do you concur?
>
> Best regards,
>
> Sherman Chen
> Signal Integrity
> EMC Global Hardware Engineering
> Tel: +86 21 60951100ext3329
>
> From: Nathan JP [mailto:jpnathan@xxxxxxxxxxx]
> Sent: Wednesday, July 02, 2014 2:49 AM
> To: Chen, Sherman; si-list@xxxxxxxxxxxxx<mailto:si-list@xxxxxxxxxxxxx>
> Subject: RE: [SI-LIST] HBA PCIe gen2 test w/o using CBB
>
> Hi Sherman,
>
> The below given set-up should be ok for measuring the gen-2 signal
> quality transmitted from PCIe card.
>
> Note:
> Assuming that the Compliance test pattern is forced from the PCIe device in
> HBA card.
> Also, if the HBA card uses a local Ref-Clk, it's Clk Jitter can be measured
> separately. Else, a low jitter external Ref-Clk need to be fed.
>
> CEM 2.0 Tx spec (for Add-in Card) can be used for measuring gen-2 express
> card signals quality (either in Scope SW or with Sigtest tool).
>
>
> Regards,
> Nathan JP
> ________________________________________
> From: Chen, Sherman
> Sent: ý01-ý07-ý2014 22:07
> To: si-list@xxxxxxxxxxxxx<mailto:si-list@xxxxxxxxxxxxx>
> Subject: [SI-LIST] HBA PCIe gen2 test w/o using CBB
> Dear PCIEers,
>
> I believe in this list there are quite a lot of experts who have deep
> understanding on PCIe spec. as well as test practice. So here is my question:
>
> We are thinking to evaluate the gen2 signal quality as well as the REF_CLK of
> one HBA card. For some reason we don't plan to use CBB unless we have to.
> Thus the test procedure has to be altered on some aspects. Mainly they are:
> 1. the test point is at the PCIe connector rather than SMP or REF_CLK
> connector.
> 2. the connection means is changed from SMP2SMA adaptor + SMA cable to
> diff probe.
> The captured waveform will be fed into Sigtest/PCIe clock jitter tool to
> generate the test result.
>
> Will above method still give a result very close to the result obtained by
> using CBB? Personally I don't see big difference will be produced here...
>
> And, if we drops Sigtest/jitter tool, and use scope to measure the
> EH/EW/Jitter. What criteria shall we follow - CEM3.0 TX/RX spec.?
>
>
> Best regards,
>
> Sherman Chen
> Signal Integrity
> EMC Global Hardware Engineering
> Tel: +86 21 60951100ext3329
>
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