[SI-LIST] Fwd: Re: PCB too small for adequate plane capacitance
- From: steve weir <weirsp@xxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Thu, 08 Jan 2004 12:10:38 -0800
>Date: Thu, 08 Jan 2004 10:42:33 -0800
>To: peter.baxter@xxxxxxxxxxxxx, <si-list@xxxxxxxxxxxxx>
>From: steve weir <weirsp@xxxxxxxxxx>
>Subject: Re: [SI-LIST] PCB too small for adequate plane capacitance
>
>Peter, are those transmission lines going off-board? If so, then try and
>look at this systemically with the daughter card mounted.
>
>Lots of BC layers tend to lose their effectiveness as you move down the
>PCB stack. The evil of inductance bites you once again.
>
>2 sq inches doesn't provide a lot of BC. Even if you go to a high K
>material and 1 mil thickness you are going to have more than 100
>milliohms impedance at 200MHz after accounting for anti-pads. If you are
>using FR4, and 3mils, the BC for such a small area is going to yield 1.5
>to 2 ohms at 200MHz. I don't know how many "a whole series" is, but you
>can see that the insertion loss will be limited.
>
>Things you can do off-hand:
>
>1) If you can, limit the rise-time of the signals with the driver device.
>
>2) If possible, flood the component layer with ground, and stack-up as:
>
>L1 ground flood / component
>High K
>L2 power
>High K
>L3 ground
>
>L4 signal E-W
>
>L5 signal N-S
>
>L6 power
>High K
>L7 ground
>High K
>L8 power flood
>
>3) Use high K thin material from L3 to L4, L4 to L5 and L5 to L6. This
>will impose some loss on your 200MHz signals, but that will generally be a
>good thing. You aren't going to see much loss on a 1" X 2" board
>anyway. The high K material in these layers will not increase the
>capacitance by much. If you need more routing layers, build-up
>symmetrically in the center. One more pair of routing layers would make a
>12 layer board.
>
>4) Use IDC or X2Y caps for your decoupling to the planes. Make sure to
>mount these on L1.
>
>Both types have very low inductance. The problem with IDC's is managing
>those micro-vias on 0.8mm centers. If you board is thin enough to use
>micro-vias, or you sequentially laminate microvia L1 to L3 to the
>remaining layers IDCs are a viable choice. If you move fan the vias to
>use mechanical drills, you largely defeat the low inductance of the IDC
>design. If cannot use micro vias as needed with IDCs, then X2Ys are the
>capacitors of choice.
>
>5) Make sure you have adequately bonded the daughter card returns to the
>mother card.
>
>6) Aggressively decouple the motherboard that this assembly connects to.
>
>7) Use BC on the motherboard as in 3) to take the edge off of those signals.
>
>Steve.
>
>
>At 10:29 PM 1/8/2004 +1100, Peter Baxter wrote:
>>while the si-list is talking about power distribution...
>>
>>I have a 2" by 1" PCB that contains one IC that drives a whole set of series
>>terminated transmission lines. It always clocks data at 200MHz. Due to the
>>impedance of the transmission lines, the current required by the driver IC
>>requires there to be about 10-14 GND/POWER/GND layers, along with low
>>inductance IDC caps (for a flat impedance out to 1GHz). Buried Capacitance
>>may need to be considered, however it has been suggested that it be avoided
>>if possible.
>>
>>My basic problem is that the housing limits the size of the PCB, which
>>restricts the power plane area.
>>
>>Is there an alternative approach that I ought to consider, or have I
>>approached it the only practical way.
>>
>>Cheers,
>>
>>Peter Baxter
>>
>>
>>
>>
>>
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