[SI-LIST] Re: De-rating
- From: Siddharth Rajagopalan <maxsidhu@xxxxxxxxx>
- To: "Moran, Brian P" <brian.p.moran@xxxxxxxxx>
- Date: Thu, 31 May 2012 20:09:19 +0530
Dear moran,
Thanks for your time and effort in helping me understand
this concept, sir. while scanning through the slides, i noticed this, in
silde no.16 under the composite de-rating at AC/DC table, you said that
positive values reduces the margin. Let me consider the examples of 1v/ns
anf 2v/ns SR (for the AC175/DC 100 case.),
- DDR3-800 for 1V/ns SR,
- tls (Vref) = 375ps
- tls(AC) =( 375ps - 175ps) = 200ps
- tih (DC) = (375ps - 100ps) = 275ps
Here we have a setup margin of 200ps and a hold margin of 275ps.
- DDR3-800 for 2V/ns SR,
- tls (Vref) = 375ps
- tls(AC) =( 375ps - 87.5ps) = 287.5ps
- tih (DC) = (375ps - 50ps) = 325ps
Here we have an improved setup margin of 287.5ps and a hold margin of
325ps.
I find an increased margin in the second case. please help me correct my
understanding.
Thanks
siddharth rajagopalan
On Wed, May 30, 2012 at 10:27 PM, Moran, Brian P <brian.p.moran@xxxxxxxxx>wrote:
> Siddarth,
>
> Here are some slides on derating. The derating table in JEDEC SDRAM spec
> is
> actually a combination of two effects. Actual derating of SDRAM timing is
> actually
> a small contributor in most cases and only impacts SDRAM timing below
> 1V/ns. Basically its
> considered timing guardbnad for low edge rates, due to a number of
> reciever effects.
> It is not calculated but derived from empirical tester data. The othe
> reffect is what
> I call threshold normaization or compensation. This has to do with the
> change from
> measuring timing at Vref, to defining timing at AC/DC thresholds. Its
> explained in the
> slides I attached. This component of derating is a simple algebraic
> formula which normalizes
> timing measured at Vref and timing measured at AC/DC, to account for
> variation
> in slew rate vs the assumed 1V/ns used to define the baseline tIS(ac) and
> tIH(dc).
>
> Its quite messy actually, and I'm not sure it is representative of real
> SDRAM operation.
> Its more of a spec consistency issue meant to keep the old Vref
> measurement method and
> the newer AC/DC methos in sync. It confuses everyone. That's why I wrote
> the slides.
> How they help.
>
>
>
> Brian Moran
> Signaling Development Group
> Client Platforms
> Intel Corporation
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of Siddharth Rajagopalan
> Sent: Wednesday, May 30, 2012 9:32 AM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] De-rating
>
> Hello everybody,
> Can someone please explain me on the relation between
> setup time, hold time and de-rating?? i did some ground reading on it and
> encountered terms like charge accumulation, dispersion. where does this
> happen??how is del(t) calculated??
> --
> Thanks in advance,
> Siddharth Rajagopalan
>
>
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--
Regards,
Siddharth Rajagopalan
Antenna Division,
R & D services,
HCL Technologies,
Ph : 9994477122
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