[SI-LIST] DSP core and I/O power pane coupling
- From: jean-pierre bouthemy <jean-pierre.bouthemy@xxxxxxxxxxxxxxxxxx>
- To: SI list <si-list@xxxxxxxxxxxxx>
- Date: Thu, 21 Jan 2010 15:00:13 +0100
Hello SI experts,
I am faced to a stackup issue for a multichip module including a DSP die
with 1.9V core and 3.3V I/O supplies.
In the stackup the 2 planes are coupled each other with about 550 pF:
Dielectric thicknesse between the 2 planes is 127µm and dielectric
constant is 9.8 (Alumina).
Coupling surface is about 80mm x 10mm.
We have thus C = 8.856* 10 * (80*10)/127 = 547pF
1.9V DSP core PDS impedance is in the order of 2 ohms (estimated from
decoupling study).
Noise on 3.3V power plane can be in the order of 100mVpp.
=> Do you think it can be an issue for noise coupling from 3.3V I/O
plane to 1.9V plane?
=> I suppose noise coupling from 1.9V to 3.3V power plane shouldn't be a
problem, do you agree?
Thank you for your answers.
Regards.
JP Bouthemy
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