[SI-LIST] Re: DDR3 VTT Accuracy Requirements
- From: Shawn Wang <ShawnWang@xxxxxxxxxx>
- To: Hirshtal Itzhak <ihirshtal@xxxxxxxxxx>, si-list@xxxxxxxxxxxxx
- Date: Thu, 25 Mar 2010 21:06:54 +0800
hi,
Here is my opinion:
In one's common sense, it's a good idea to set a same voltage (usually Vddq/2)
for both Vref and Vtt to get the best margin. But maybe it's not ture. The
design of DDR3 interface is very flexible. It allows you to adjust Vref voltage
by more than 150mV for obtaining the best margin while keeping Vtt voltage
fixed. So Vtt voltage needn't to track the change of Vref.
----- Original Message -----
From: "Hirshtal Itzhak" <ihirshtal@xxxxxxxxxx>
To: <si-list@xxxxxxxxxxxxx>
Sent: Thursday, March 25, 2010 4:31 PM
Subject: [SI-LIST] Re: DDR3 VTT Accuracy Requirements
> Hello again!
>
>
> Since no-one answered, I re-send my question, in case there was some
> problem which prevented many of you from seeing my question.
>
>
>
> Thanks again
>
>
>
> Itzhak
>
>
>
> ________________________________
>
> From: Hirshtal Itzhak
> Sent: Monday, March 22, 2010 3:49 PM
> To: si-list@xxxxxxxxxxxxx
> Subject: DDR3 VTT Accuracy Requirements
>
>
>
> Hello,
>
>
>
> I've noticed lately that VTT specification for the DDR3 SDRAM devices is
> not defined as was VTT for DDR2 devices.
>
>
>
> For the DDR2 devices it was required to be no further than 40mV from
> VREF.
>
>
>
> In the DDR3 spec this requirement has been removed and instead a note
> says that the MIN & MAX values for this supply are system dependent.
>
>
>
> What system considerations are to be applied for VTT tolerance? The only
> thing that comes to my mind is the timing of the ADR/CMD signals. Would
> simulations with the "skewed" VTT be enough to evaluate the impact of
> certain VTT in-accuracies? Can I assume (as a 1st degree assumption)
> that the in-accuracy of VTT will be directly reflected in the threshold
> levels of the device?
>
>
>
> And are there other considerations to be taken?
>
>
>
> Thanks in advance
>
>
>
> Itzhak Hirshtal
>
>
>
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