[SI-LIST] DDR3 Timing Webinar - registration information
- From: Brad Griffin <bgriffin@xxxxxxxxxxx>
- To: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Mon, 7 Jun 2010 10:11:46 -0700
Hi,
We had reached the capacity for our free June 9th webinar, "Addressing DDR3
Timing Challenges", but more space has been added. If you had trouble
registering, please retry at http://www.secure-register.net/flyer.php?id26.
This webinar features integration between TimingDesigner and Cadence Allegro
PCB SI as part of a comprehensive DDR3 design and analysis solution.
Please contact me off the list if you have any questions.
Best regards,
Brad Griffin
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