[SI-LIST] DDR3 FAQs
- From: "Katkoria, Deepak" <Katkoria.Deepak@xxxxxxxxxxx>
- To: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Tue, 24 Aug 2010 09:36:31 +0200
1. What are electrical factor to assign/place a test points on the
net.(size, type, SI issues) On my board, TP are so small that its hard to
solder the Agilent differential probes.
2. Any suggestion on how to probe the DDR3 signals. Agilent DDR3 socket
are hard to solder(PCB manufacture issue), so I am avoiding it..
3. Any PCB guideline for DDR3 interface
4. Any experience or comment on Agilent Automated test application for
DDR3 test?
5. To measure a tDS & tDH, why we need to calculate two different slew
rate(rising & failing)?
6. Can I consider a derating value for DDR3-1333 tDS/tDH to be same for
each data lane? ( I have to measure a data line from each lane to find out the
derating value of that lane)
7. Similarly can I consider the derating for tIS/tIH would same all
address/cmd line?
Cheers,
Deepak
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