[SI-LIST] Re: DDR2 spacing rule
- From: "Mustafa Yousuf" <yousufs432@xxxxxxxxx>
- To: <balaseven@xxxxxxxxx>, "'Prashant Jaiswar'" <prashant.jaiswar@xxxxxxxxx>
- Date: Sun, 28 Jul 2013 15:46:04 -0700
Hi Bala,
Not trying to repeat what was said but to perhaps put more clearly.
Each byte is associated with its own DQS and must be length matched
accordingly within the byte.
DQS's need not to be length matched tightly together but they need to remain
length matched to CLK within 1/4 CLK cycle.
Each bye with its DQS could be toggling differently from other bytes and
could be routed in different location or even different layer from other
bytes. This means exposure of each byte to different crosstalk (XTalk)
environment although XTalk should be minimized for each byte. Hence byte to
byte spacing should be as large as possible and larger than trace to trace
spacing within the byte. This is to minimize XTalk between bytes which helps
maintain timing control for the entire bus.
I hope this helps.
Regards,
Mustafa
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of bala
Sent: Sunday, July 28, 2013 11:10 AM
To: Prashant Jaiswar
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: DDR2 spacing rule
Hi Prashant,
How it helps to meet timing budget..some slight timing pull-in/out might be
there due to crosstalk..how this crosstalk varies w.r.t byte to bye..We are
allowed to have 2X spacing for same data byte but 3X needed for different
byte...Though DQS is different,data is running at same frequency and
delay.How/Why there is a difference in xtalk amplitude?Thanks for your time.
Regards
bala
On Sun, Jul 28, 2013 at 10:06 PM, Prashant Jaiswar <
prashant.jaiswar@xxxxxxxxx> wrote:
> DQS is defiend per byte lane and the data is sampled with respect to
> DQS of each byte lane during read/write operations.
> This helps meet the timing budget/relationship from DRAM
> controller/memory chip per se.
>
> On Sun, Jul 28, 2013 at 2:55 PM, bala <balaseven@xxxxxxxxx> wrote:
>
>> Hi All,
>> Why data lines of same byte in ddr2 routed together?As we know all
>> the data lines in a DDR2 running at same frequency and if we route
>> byte0 and byte1 at same length,why do we need to maintain different
>> trace-trace spacing for same byte and different byte?
>>
>> --
>> bala
>>
>>
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>
>
> --
> The only good is knowledge and the only evil is ignorance
--
bala
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