[SI-LIST] Re: DDR-2 address Termination Topology

I'm reminded of a biblical reference.......
Give a man a termination and terminate him for a day
or project.  Teach a man to terminate and he can terminate
for a lifetime.

If you really want it this easy, then I humbly suggest that
you talk to your memory controller supplier and as him for
the memory interface design guidelines.  They will give you
board impedance requirements, routing guidelines (length
matching, etc) and the termination scheme.

Should you see the latter, then I humbly suggest that you
make use of google as there are a number of fantastic docs
available to explain the whys of DDR2 address and other
termination.  I also humbly suggest you research ODT as
that has quite a bit to do with how the data lines can work
properly and why it was included from DDR to DDR2.

FYI, and FWIW.  That is all...........

-Michael.

And all this science they don't understand
Is just my job six days a week.....

We will either find a way or make one   -Hannibal

In the middle of every difficulty lies opportunity   -Al Einstein
On Thu, Mar 11, 2010 at 9:23 AM, Ragesh <rageshmb@xxxxxxxxx> wrote:

> Hi Guru's,
> Which is the preferred termination for DDR-2 address lines? the
> configuration is 2 devices sharing address lines.
>
> 1) One 50E parallel termination to Vtt at the split.
> 2) Two 100E resistors each at the devices.
>
> The maximum length for any address line is less than 2 inches and the DDR-2
> frequency is 533.
>
> Reagrds
> RaGZ & AVM
>
>
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-- 
Best Regards,

Michael C. Greim


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