It looks like you'll need to use one of these:
http://www.corelis.com/products-JTAG/Hardware_JTAG_IO_Modules.htm
"The SCANIO family of products use boundary-scan gate arrays to add control and
visibility to connectors, traces, and logic that can not be tested using
traditional boundary-scan techniques."
You could also plug known good memory DIMMs into your DIMM connectors, and use
a Corelis memory test.
-John Zelno
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On ;
Behalf Of Lakshmi Narayanan Sowrirajan, ERS-HCLTech
Sent: Sunday, June 12, 2016 10:13 PM
To: si-list@xxxxxxxxxxxxx
Cc: Lakshmi Narayanan Sowrirajan, ERS-HCLTech
Subject: [SI-LIST] Corelis Boundary Scan Testing tool support
Importance: High
Dear Team,
Good morning.
I need support on CORELIS tool, I understand that it is not related to this
list. But am not able to get any support from this tool vendor, that's why I am
writing here.
In my design I have DIMM connectors connected to Xilinx FPGA. I want to model
the connector so that the nets are included in my boundary scan testing.
Similarly I do have PCIe connectors in my design.
So please let me know how can I model connectors with Corelis TPG tool.
Thanks in advance.
Regards
SLN
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