[SI-LIST] Re: Cisco Opportunities
- From: "Tomas Diaz -X (todiaz - Spherion at Cisco)" <todiaz@xxxxxxxxx>
- To: "Sherry Brock (shbrock)" <shbrock@xxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Fri, 8 Jul 2011 15:58:17 -0700
Thank you for posting this for us Sherry,
tomas
Tomas Diaz, SPHR
Sr. Talent Acquisition Consultant
Americas CDO Staffing Team
408.853.3451 office
todiaz@xxxxxxxxx
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Sherry Brock (shbrock)
Sent: Wednesday, July 06, 2011 12:27 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Cisco Opportunities
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Cisco is seeking a Senior Signal Engineer in the San Jose area. This is
working in a start up environment, fast paced environment that will
allow you to contribute to development of next generation products in
the Data Center space.=20
=20
Interested on have referrals? Please send to shbrock@xxxxxxxxx
=20
Senior Signal Integrity Engineer=20
Location: San Jose, CA
We are looking for candidates who strive in a fast paced start-up like
environment. You will be part of a dedicated team, open communications,
empowerment, innovation, teamwork and customer success are the
foundations of the team. Thus, you set your own limits for learning and
achievements.
We are looking for a motivated Signal Integrity Engineer to contribute
to the development of our next generation product.
http://www.cisco.com/en/US/products/ps10265/index.html
Job Requirements:
- Five plus years of experience in signal integrity
- Hands on person who can do both simulations and lab measurements to
validate the simulation results
- Familiar with multi gigabit serial busses, including PCIe, XAUI, KR,
XFI, and SFI
- Contribute to the signaling and interconnect technology selection
- Definition and simulation of high speed interconnects using simulation
tools
- Familiar with simulation tools such as ADS, Hspice, SpectraQuest, and
CST
- Assess timing, noise margin, crosstalk, signal loss and signal
integrity of all clocks and critical data signaling and develop noise
and timing budgets.
- Has done validation of simulations results using TDR, Network
Analyzer, Oscilloscopes and other lab equipments
- Familiar with package and board co-design methodology
- Has done Package and system level power integrity design methodology
- Backplane design experience and analog circuit knowledge are preferred
- Familiarity with high speed I/Os such as HSTL, SSTL, LVDS, LVPECL, and
serial busses
- Familiar with Memory technologies such as DDR is prefered
- Ability of working effectively with other disciplines a must
- Excellent documentation, communication skills,=20
- Effective interaction with other engineering discipline skills a
must=20
- Minimum of 5+ years of relative experience with MSEE, PHD
preferred.=20
=20
=20
=20
=20
=20
=20
Sherry Brock
Talented Search Recruiter
Americas Staffing Team, CS
shbrock@xxxxxxxxx <mailto:shbrock@xxxxxxxxx>=20
Phone: +1 919 392 5794
Cisco Systems, Inc.
Kit Creek Road, Bldg 3, 2nd floor
Research Triangle Park NC, 27709
United States
Cisco.com <http://www.cisco.com/>=20
http://www.facebook.com/pages/Cisco-Sales-and-Services-Jobs/119480978095
283
<http://www.facebook.com/pages/Cisco-Sales-and-Services-Jobs/11948097809
5283>=20
CHECK OUT OUR AWESOME CUSTOMER SOLUTIONS JOBS FAN PAGE and BECOME A FAN!
<http://www.facebook.com/pages/Cisco-Sales-and-Services-Jobs/11948097809
5283>=20
=09
Think before you print.
Cisco Systems, Inc.=20
Registration Address: 170 West Tasman Drive,=20
San Jose, CA 95134=20
Place of Registration: California, USA
For corporate legal information go to:
http://www.cisco.com/web/about/doing_business/legal/cri/index.html
<http://www.cisco.com/web/about/doing_business/legal/cri/index.html>=20
=20
=20
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