[SI-LIST] Re: Can SSN be restrained by board decaps?
- From: "DAVID CUTHBERT" <telegrapher9@xxxxxxxxx>
- To: xuzhengrong <Zhengrong.Xu@xxxxxxxxxx>
- Date: Wed, 7 May 2008 07:09:45 -0600
You can view the power bus noise by soldering a coaxial cable to the power
bus VSS-VDD. Insert a 50 ohm series resistor in the center conductor. Set
the oscilloscope to AC coupling.
The noise may be internal to the IC and external decoupling capacitors will
not help much. The internal GND bounce on the die might be the biggest issue
and may be several hundred millivolts. This modulates VREF and will cause
timing jitter. The die can be viewed, although in a system this can be
difficult. The measurement involves viewing the die through one of the DQ's.
So you can measure and quantify all of this but there might not be much you
can do to improve things.
Dave Cuthbert
Focused Test, Inc.
On Tue, May 6, 2008 at 10:19 PM, xuzhengrong <Zhengrong.Xu@xxxxxxxxxx>
wrote:
> Hi all,
> In a test, I find there are large ringings on some DDR control signals
> occasionally.
> According to the timing diagram, I suspect SSN leads to the large ringing.
> And the spice simulation result which I imitate SSN mechanism looks like
> the
> test waveforms.
> I think there is a resonance generated by C_die and package parasitics
> (L_pkg dominantly).
> I derive the resonance frequency from the ringing period and add several
> corresponding decaps near the chip for improving the PDN.
> It seems these decaps hardly have effect on SSN.
> Since the L_pkg is usually about 10nH if the package is bad designed, it
> almost separate the effect of PDN on die side from board decaps on mega
> Hz,
> can the resonance be improved by board caps?
> Appreciate any idea that those have experience on SSN and PDN co-design
> could share.
>
> Best Regards,
> Zhengrong
>
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