[SI-LIST] Re: Book - "Signal Integrity for PCB Designers" offered at low cost
- From: V S <for_si2003@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Fri, 23 Oct 2009 16:46:30 -0700 (PDT)
I have about 18 copies of "Signal Integrity for PCB Designers" left that I am
offering at $25. You may like to buy your copy at
http://www.amazon.com/gp/offer-listing/0982136900
It will be shipped out before Saturday noon, if I receive response by Saturday
forenoon.
Best Regards,
Vikas Shukla
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of V S
> Sent: Monday, October 19, 2009 8:32 AM
> To: SI LIST
> Subject: [SI-LIST] Book - "Signal Integrity for PCB
> Designers" offered at low cost
>
> I have 50 copies of my book "Signal Integrity for PCB
> Designers" available from my publishers. I am offering these
> books at price of $25 at amazon under used books (even
> though they are new ones).
>
> You may like to purchase these at the discounted price at
>
> http://www.amazon.com/gp/offer-listing/0982136900
>
>
> I hope that this book is helpful for beginners. The
> contents are as follows
>
> Table of Contents
>
> 1 Introduction.. 4
> 1.1 Integrity of Point to Point Signal 5
> 1.2 Timing Relationship between Signals. 6
> 1.3 Coupling of the traces. 6
> 1.4 Noise less Power supply. 7
> 1.5 Electromagnetic Radiation. 7
> 1.6 PCB Design for High Speed. 7
> 1.7 Knee Frequency. 12
> 1.8 Periodic Waves and Fourier Transform.. 12
> 1.9 Tom and Bob. 16
> 2 Timing Relationship between Signals. 17
> 2.1 Setup and Hold Time. 17
> 2.2 Time and Distance. 18
> 2.3 Adding Delay Intentionally.. 20
> 2.4 Common Clock Vs Source Synchronous Clock Scheme. 21
> 2.5 Incident Clocking. 23
> 2.6 Implementation. 23
> 2.7 Length Matching examples - PCI Bus Clocks. 24
> 2.8 Tom and Bob. 24
> 2.9 Questions and Answers. 26
> 3 Resistor and Resistance. 27
> 3.1 Parasitic Inductance and Capacitance of SMD Resistors.
> 29
> 4 Capacitance and Capacitor. 30
> 4.1 Parallel Plate Capacitor 31
> 4.2 Impedance of a Capacitor 32
> 4.3 Capacitance in a Signal Path. 33
> 4.4 A Real Capacitor 33
> 4.5 Capacitance per unit length. 34
> 4.6 Capacitance Per Unit length of a Coaxial Cable. 34
> 4.7 Capacitance per Unit Length of a Microstrip. 35
> 4.8 Effective Dielectric Constant 36
> 4.9 Embedded Microstrip Trace. 37
> 4.10 Stripline Trace. 38
> 4.11 2D Field Solver for Calculating Capacitance. 39
> 4.12 Accuracy of IPC Formula with respect to the 2D Field
> Solver 40
> 4.13 Fringe Effect and Capacitance of Combination of
> structure. 42
> 4.14 Via Capacitance. 43
> 4.15 Questions and Answers. 44
> 5 Inductance. 46
> 5.1 Origin of Inductance. 46
> 5.2 Magnetic Flux. 47
> 5.3 Definition and Calculation of Inductance. 47
> 5.4 Magnetic Field Line Loops. 48
> 5.5 Inductance of Isolated Structure. 48
> 5.6 Mutual Inductance. 50
> 5.7 Changing Magnetic Field and Induced EMF. 51
> 5..8 Total Inductance. 52
> 5.9 Impedance of a Inductor 54
> 5.10 Questions and Answers. 54
> 6 Power Planes. 56
> 6.1 Need of Multilayer Board. 56
> 6.2 Power Plane for Impedance Requirements. 56
> 6.3 Power Plane for Power Supply Requirement 56
> 6.4 Tight Coupling and Crosstalk requirements. 57
> 6..5 Power Plane and Stitching Capacitors. 57
> 6.6 A typical 4 Layer stack up. 57
> 6.7 A typical 6 Layer stack up. 57
> 6.8 A typical 8 Layer stack up.. 59
> 6.9 Symmetry and Board Warping. 60
> 6.10 Tom and Bob. 60
> 7 Power Supply. 62
> 7.1 DC Perspective. 62
> 7.2 Power Supply - The AC Perspective. 64
> 7.3 Inductance of Power Supply Wiring. 67
> 7.4 Minimum Impedance Requirement of an IC with IO gates
> switching. 68
> 7.5 How to achieve low impedance. 71
> 7.6 Series Inductance of Bypass Capacitor and need for
> local capacitor.. 72
> 7.7 Find the Impedance profile of power supply. 72
> 7.8 Capacitance of Power-Ground Plane. 74
> 7.9 Tom and Bob. 75
> 8 Differential Signaling.. 86
> 8.1 Advantages of Differential Signaling. 86
> 8.2 Immunity from Ground Noise. 86
> 8.3 Power saving by use of small voltage.. 87
> 8.4 High Data Speed Possible. 87
> 8.5 Immunity to Crosstalk / Electromagnetic interference.
> 87
> 8.6 Rules for Differential Signal Routing. 87
> 8.7 Differential Impedance. 88
> 8.8 Microstrip Differential impedance. 88
> 8.9 Stripline Differential impedance. 89
> 8.10 Crosstalk in Differential Signaling. 90
> 8.11 HyperTransport - A case study. 90
> 8.12 Routing Differential Signals on PADS Router©.. 92
> 8.13 Differential Impedance Calculator Using HSPICE 2D
> Field Solver 97
> 8.14 Never Rely completely on automatic Design Rule tester
> 99
> 8.15 Questions and Answers. 100
> 9 Transmission Line. 101
> 9.1 When is Transmission Line essential 101
> 9.2 Properties of Transmission Lines. 102
> 9.3 Capacitance and Inductance Per Unit length of the
> Transmission Lines. 102
> 9.4 Propagation Delay. 103
> 9.5 Characteristic Impedance. 104
> 9.6 Impedance Calculator for Microstrip. 105
> 9.7 Impedance Calculator for Stripline. 109
> 9.8 A Comparison of the IPC Calculator, Wadell Formula and
> 2D Field Solver 111
> 9.9 Impedance Calculations and Verification from within
> PADS. 112
> 9.10 Impedance Calculations and Verification from within
> Allegro. 117
> 9.11 The Return Path on a Transmission Line. 123
> 9.12 Impedance between power Planes. 126
> 9.13 Reflections from Capacitive discontinuity. 127
> 9.14 Effect of Incident Signal Rise time. 128
> 9.15 Effect of the Capacitance Value on reflection. 129
> 9.16 Effect of Impedance on Reflection. 131
> 9.17 Compensating small Inductive or Capacitive
> discontinuity. 132
> 9.18 Calculating the length of the thin trace. 135
> 9.19 Thin Traces at breakout region. 140
> 9.20 The reflection Coefficient 141
> 9.21 Input Acceptance voltage. 142
> 9.22 The Source and Load impedance. 143
> 9.23 Source Termination. 144
> 9.24 End Termination. 145
> 9.25 Reflection from Capacitive Loads. 145
> 9.26 Transmission Line - An intuitive approach. 145
> 9.27 Losses in Transmission Lines. 146
> 9.28 Resistive Losses. 146
> 9.29 Estimation of Resistive loss for High Frequency
> Signals. 146
> 9.30 The Power ratios in dB.. 148
> 9.31 Expression of Power in Absolute Unit - dBm.. 149
> 9.32 Power gain in nepers. 150
> 9.33 Power Ratio in dB in terms of voltage ratio. 151
> 9.34 Expression of Voltage in Absolute Unit - dBmV.. 151
> 9.35 Expression of Voltage in Absolute Unit - dBμV.. 151
> 9.36 Skin Effect 152
> 9.37 Skin Depth. 153
> 9.38 Effect of Surface Roughness on Signal Loss. 154
> 9.39 Dielectric Losses. 154
> 9.40 Radiation and Induction Losses. 155
> 9.41 Questions and Answers. 155
> 10 Simulation using Hspice. 157
> 10.1 Reflected Wave Simulation. 159
> 10.2 Effect of Source Impedance. 160
> 10.3 Effect of Capacitive discontinuity. 162
> 10.4 Parameter in hspice. 163
> 10.5 Parameter sweep.. 164
> 10.6 A 2D Field Solver using HSPICE.. 165
> 10.7 Inductance of a trace - an interesting rule of thumb.
> 171
> 10.8 Power Plane Inductance. 173
> 11 Crosstalk. 177
> 11.1 Inductive Coupling or Crosstalk. 177
> 11.2 How to avoid Inductive Crosstalk. 177
> 11.3 Capacitive Coupling or Crosstalk. 177
> 11.4 How to avoid capacitive Coupling. 178
> 11..5 Directionality of Crosstalk. 178
> 11.6 Near End Cross talk. 179
> 11.7 Effect of Trace separation on NEXT signal amplitude.
> 180
> 11.8 Effect of separation from Power Planes. 185
> 11.9 Microstrip Vs Stripline.. 187
> 11.10 Far End Cross Talk. 189
> 11.11 Variation with rise time. 191
> 11.12 Variation with length. 192
> 11.13 A formula for the Far End Cross Talk Ratio. 193
> 11.14 Stripline and FEXT. 194
> 11.15 Reducing FEXT. 194
> 11.16 Guard Traces. 194
> 11.17 Practical Considerations for routing Guard Traces.
> 196
> 11.18 Questions and Answers. 197
> 12 Characterization of High Speed Bus. 200
> 12.1 Correlating Simulation Result with Characterization
> Results. 200
> 12.2 Characterizing voltage margin. 201
> 12.3 Characterizing frequency margin. 201
> 12.4 Oscilloscope. 202
> 12.5 Time Domain Reflectometer 205
> 12.6 Jitter 206
> 13 Designing for EMI Compliance. 209
> 13.1 An Approximation of Electric Field from A Current Loop
> Antenna. 212
> 13.2 What Causes EMI. 213
> 13.2.1 Cables. 214
> 13.2.2 Field induced in cables. 214
> 13.2.3 Clock Oscillators. 215
> 13.2.4 Mismatched Transmission Line. 215
> 13.2.5 Long Traces. 215
> 13.3 How to Reduce EMI. 215
> 13.3..1 Match the Transmission Line and Termination. 215
> 13.3.2 Use Short Clock Lengths where possible. 215
> 13.3.3 Use Differential Signaling. 215
> 13..3.4 Use Higher value of Series Resistor 216
> 13.3.5 Use Stripline over Microstrip for Critical Nets.
> 217
> 13.3.6 Board level Shielding. 217
> 13.3.7 Use Lower Voltage Swing. 217
> 13.3.8 Do not route Critical Signals near edges. 218
> 13.3.9 Use of Metallic Shields or Enclosures. 218
> 13.3.10 Shield Conductive Coating. 218
> 13.3.11 Use of Spread Spectrum Oscillators. 219
> 13.4 Conducted Emission. 220
> 13.5 Doing your own EMI analysis. 220
> 13.6 Question and Answers. 224
> 14 Signal Integrity Tips. 225
> 14.1 Tips for Integrity of Point to Point Signal 225
> 14.2 Tips for Cross talk Reduction. 226
> 14.3 Tips for Power Supply Noise Reduction. 227
> 14.4 Tips for EMI Reductions. 227
> 15 Shielding.. 229
> 15.1 Reflection. 230
> 15.2 Absorption loss. 232
> 15.3 Effect of Apertures. 234
> 16 Miscellaneous SI Topics. 236
> 16.1 Pre-emphasis. 236
> 16.2 Cable Twisting. 236
> 16.3 Package Model 237
> 16.4 Models and Modeling. 239
> 16.5 Right Angle PCB Bend. 241
> 16.6 Via. 243
> 16.7 Insertion of Guard Band to reduce cross talk. 243
> 16.8 Differential Pairs - coupling tight or not 244
> 16.9 Magic Capacitors. 245
> 16.10 PCI Bus. 246
> 16.11 Using Blind Vias in BGA based PCB Design. 248
> 16.12 BGA, Blind via and Via in Pad. 249
> 16.13 Consideration for Mixed PADs with and without Vias.
> 250
> 16.14 Blind Via and aspect ratio. 250
> 16.15 Relation between BGA pitch and pad size. 250
> 17 Questions and Answers. 252
> 18 References. 262
> 19 Index
>
> Vikas Shukla
>
>
>
>
>
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