[SI-LIST] BER and Adaptive Equalization
- From: Kai Keskinen <KKeskinen@xxxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Tue, 11 Sep 2001 08:03:03 -0400
Hello SI Folks:
This question is in the general line of the 8b/10b trail.
I know how BER can be calculated from the eye diagram for standard logic
where the chip switches from high to low or vice versa at some given
voltage. Over a given link, as the eye gets smaller, the BER goes up. How
does one deal with adaptive equalizer chips? In our experience, in one case,
we can have a totally closed eye at the receive pads and with the equalizer
chip get an acceptable BER. In the next case, we also have a closed eye at
the receive pads and we get a very high bit error rate. In both cases, the
eye from the equalizer chip output looks good but it is losing transitions
in the high BER case. I'm really interested in the behaviour of the chips in
the presence of cross-talk and reflections for which the equalization
doesn't work well. Does anyone know of any references to these topics or
have any quantifiable data?
Thanks,
Kai Keskinen
Signal Integrity Advisor
C-MAC Engineering Inc.
425 Legget Drive
Kanata, ON K2K 2W2
kkeskinen@xxxxxxxxxxx
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