[SI-LIST] Re: AW: 8-Layer asymmetrical Stackup
- From: Istvan Novak <istvan.novak@xxxxxxx>
- To: "Havermann, Gert" <Gert.Havermann@xxxxxxxxxxx>
- Date: Wed, 30 Sep 2009 08:05:42 -0400
Another factor to consider is the very strong coupling between the
outside layers. Pads and escape traces on the top/bottom layers will
couple to the signal layers below/above, and keep in mind that regular
pads look gigantic compared to usual traces, so the localized coupling
will be very strong. And not having another ground layer to attract the
stray fields, the horizontal range for the coupling is bigger. With low
component density on the top/bottom sides and/or having lower-speed
signals on the board, this stackup may work. Otherwise a more detailed
analysis is warranted.
Regards,
Istvan Novak
SUN Microsystems
Havermann, Gert wrote:
> If you are using prepregs and laminates of equal thickness, and have a lot of
> copper on all signal layers, Then depending on the ammount of copper and the
> routing direction on the Signal Layer you might be able to get around warpage
> issues (good luck).
> You should be very careful with running high speed signals on L2 and L7. the
> copper flood on the component layer will have a lot of openings where the
> solder pads are, these are discontinuities in the GND return path.
>
> BR
> Gert
>
>
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> -----Ursprüngliche Nachricht-----
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> Von: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] Im
> Auftrag von Embedded
> Gesendet: Montag, 28. September 2009 11:10
> An: si-list@xxxxxxxxxxxxx
> Betreff: [SI-LIST] 8-Layer asymmetrical Stackup
>
> Dear Experts,
> In our dsign,we need minimum 5-signal layers including top and bottom layers.
> I can use blind via from L1 to L2 only. The blind via from L1 to L3 is not
> allowed.
> So we have to assign signal layers adjacent to top and bottom layer.
>
> So considering all these constraints,I am planning to use the following
> 8-Layer stackup.
>
> Stackup
> --------
> L1 --- Top (Signal/ Component)
> L2 --- Signal
> L3 --- Plane (VCC1)
> L4 --- Signal
> L5 --- Plane (GND)
> L6 --- Plane (VCC2)
> L7 --- Signal
> L8 --- Bottom (Signal / Component)
>
> The board thickness is 1mm. This stackup is not symmetrical. The Layer L4 and
> L5 are unbalanced.
>
> We would like to know that in this stackup will there be any issue like PCB
> Warpage and Yield in board proto and production build?
>
> Ans also let me know your feedbacks on the stackup.
>
> Thanks in Advance
> MR
>
>
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