[SI-LIST] Re: 4layer board stack up for PCI boards

On 27 Sep 01 at 12:52, GOPALCHETI,MANOJ (HP-Cupertin wrote:

[....] 
> 1. With Power and Ground plane closer and far from signal layers
> Signal Layer 1.5Oz, 8 mil trace
> Dielectric 26mils
> Plane Layer 1.00oz
> Dielectric 8mils
> Plane Layer 1.00oz
> Dielectric 26mils
> Signal Layer 1.5Oz, 8 mil trace
with FR4 er=4.2 about 110 Ohm

> 2. With Power and Ground plane separated far but closer to signal layers.
> Signal Layer 1.5Oz, 8 mil trace
> Dielectric 20mils
> Plane Layer 1.00oz
> Dielectric 16mils
> Plane Layer 1.00oz
> Dielectric 20mils
> Signal Layer 1.5Oz, 8 mil trace
about 100 Ohm.

Nevertheless, I'd prefer Stackup 1. Better broadband decoupling of 
VCC/GND. Perhaps consider decreasing inner dielectricum down to 4 
mit. That's much better. If necessary, fatten these traces where the 
impedance value ist important (mostly the stuff which goes out to the 
bus).  

Regards
Matthias Mansfeld
-----------------------------------------------
Matthias Mansfeld Elektronik
* Printed Circuit Board Design and Assembly
Am Langhoelzl 11, D-85540 Haar, GERMANY
Phone: +49-89-4620 0937, Fax: +49-89-4620 0938
E-Mail: m.mansfeld@xxxxxxxxxxxxxxxxxxxxxx
Internet: http://www.mansfeld-elektronik.de
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